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soc/intel/baytrail/cpu.c: Align with Braswell 

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: I52d58c6b77cd870b5d3f5892521e4c82027c4cac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43190
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-07 17:36:08 +02:00
parent 06e44a862e
commit b046bfa830
1 changed files with 11 additions and 13 deletions
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24
src/soc/intel/baytrail/cpu.c
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@ -23,8 +23,8 @@
const struct reg_script core_msr_script[] = { const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
REG_MSR_RMW(MSR_POWER_MISC, REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
/* Disable C1E */ /* Disable C1E */
REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
REG_MSR_OR(MSR_POWER_MISC, 0x44), REG_MSR_OR(MSR_POWER_MISC, 0x44),
@ -165,8 +165,7 @@ static void per_cpu_smm_trigger(void)
intel_microcode_load_unlocked(pattrs->microcode_patch); intel_microcode_load_unlocked(pattrs->microcode_patch);
} }
static void relocation_handler(int cpu, uintptr_t curr_smbase, static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase)
uintptr_t staggered_smbase)
{ {
struct smm_relocation_params *relo_params = &smm_reloc_params; struct smm_relocation_params *relo_params = &smm_reloc_params;
em64t100_smm_state_save_area_t *smm_state; em64t100_smm_state_save_area_t *smm_state;
@ -185,21 +184,20 @@ static void post_mp_init(void)
} }
static const struct mp_ops mp_ops = { static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init, .pre_mp_init = pre_mp_init,
.get_cpu_count = get_cpu_count, .get_cpu_count = get_cpu_count,
.get_smm_info = get_smm_info, .get_smm_info = get_smm_info,
.get_microcode_info = get_microcode_info, .get_microcode_info = get_microcode_info,
.pre_mp_smm_init = smm_southbridge_clear_state, .pre_mp_smm_init = smm_southbridge_clear_state,
.per_cpu_smm_trigger = per_cpu_smm_trigger, .per_cpu_smm_trigger = per_cpu_smm_trigger,
.relocation_handler = relocation_handler, .relocation_handler = relocation_handler,
.post_mp_init = post_mp_init, .post_mp_init = post_mp_init,
}; };
void baytrail_init_cpus(struct device *dev) void baytrail_init_cpus(struct device *dev)
{ {
struct bus *cpu_bus = dev->link_list; struct bus *cpu_bus = dev->link_list;
if (mp_init_with_smm(cpu_bus, &mp_ops)) { if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n"); printk(BIOS_ERR, "MP initialization failure.\n");
}
} }