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drivers/intel/fsp1_1: Remove extra include references

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Remove include references to the soc include directory which are not
required to build the FSP driver.  Remove "duplicate" include file
definitions from file that include fsp/romstage.h.  Move the definition
of fill_power_state into soc/pm.h to ensure it is still available.

TEST=Build and run on Galileo

Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy 2016-01-01 18:09:50 -08:00 committed by Leroy P Leahy
parent 98fc426a98
commit b092c9e9c1
8 changed files with 14 additions and 23 deletions
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4
src/drivers/intel/fsp1_1/include/fsp/romstage.h
View file

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
* Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -23,7 +23,7 @@
#include <fsp/car.h>
#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h> /* chip_power_state */
struct romstage_params {

5
src/drivers/intel/fsp1_1/raminit.c
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@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014-2015 Intel Corporation
* Copyright (C) 2014-2016 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -16,12 +16,11 @@
#include <cbmem.h>
#include <console/console.h>
#include <fsp/memmap.h>
#include <fsp/romstage.h>
#include <fsp/util.h>
#include <lib.h> /* hexdump */
#include <reset.h>
#include <soc/intel/common/mma.h>
#include <soc/pei_data.h>
#include <soc/romstage.h>
#include <string.h>
#include <timestamp.h>
#include <bootmode.h>

10
src/drivers/intel/fsp1_1/romstage.c
View file

@ -15,8 +15,6 @@
*/
#include <stddef.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/cbfs.h>
#include <arch/stages.h>
@ -28,17 +26,11 @@
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <elog.h>
#include <fsp/util.h>
#include <memory_info.h>
#include <fsp/romstage.h>
#include <reset.h>
#include <romstage_handoff.h>
#include <smbios.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/intel/common/util.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <soc/spi.h>
#include <stage_cache.h>
#include <timestamp.h>
#include <tpm.h>

3
src/drivers/intel/fsp1_1/stack.c
View file

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -20,7 +20,6 @@
#include <fsp/memmap.h>
#include <fsp/romstage.h>
#include <fsp/stack.h>
#include <soc/intel/common/util.h>
#include <stdlib.h>
const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;

4
src/soc/intel/braswell/include/soc/pm.h
View file

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -235,6 +235,8 @@ struct chipset_power_state {
int prev_sleep_state;
} __attribute__((packed));
struct chipset_power_state *fill_power_state(void);
/* Power Management Utility Functions. */
uint16_t get_pmbase(void);
uint32_t clear_smi_status(void);

3
src/soc/intel/braswell/include/soc/romstage.h
View file

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -33,7 +33,6 @@ void set_max_freq(void);
/* romstage_common.c functions */
void program_base_addresses(void);
struct chipset_power_state *fill_power_state(void);
int chipset_prev_sleep_state(struct chipset_power_state *ps);
#endif /* _SOC_ROMSTAGE_H_ */

4
src/soc/intel/skylake/include/soc/pm.h
View file

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
* Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -159,6 +159,8 @@ struct chipset_power_state {
uint32_t prev_sleep_state;
} __attribute__ ((packed));
struct chipset_power_state *fill_power_state(void);
/* PM1_CNT */
void enable_pm1_control(uint32_t mask);
void disable_pm1_control(uint32_t mask);

4
src/soc/intel/skylake/include/soc/romstage.h
View file

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
* Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -19,8 +19,6 @@
#include <fsp/romstage.h>
struct chipset_power_state;
struct chipset_power_state *fill_power_state(void);
void systemagent_early_init(void);
void pch_early_init(void);
void pch_uart_init(void);