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soc/mediatek/mt8192: add rtc MT6359P driver 

Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor
mt8173 and mt8183 code by extracting common API. Move rtc_read and
rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via
pmic wrapper, while mt8192 accesses it via pmif.

Reference datasheet:
  Document No: RH-D-2018-0101.

Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Yuchen Huang 2020-08-18 16:29:29 +08:00 committed by Hung-Te Lin
parent 87c30a064c
commit b0ab41e027
12 changed files with 768 additions and 135 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/soc/mediatek/common/include/soc/rtc_common.h
View File

@ -6,7 +6,6 @@
#include <bcd.h>
#include <console/console.h>
#include <rtc.h>
#include <soc/pmic_wrap_common.h>
#define RTCTAG "[RTC]"
#define rtc_info(fmt, arg ...) printk(BIOS_INFO, RTCTAG "%s,%d: " fmt, \
@ -99,29 +98,10 @@ int rtc_busy_wait(void);
int rtc_write_trigger(void);
int rtc_writeif_unlock(void);
int rtc_xosc_write(u16 val);
int rtc_lpen(u16 con);
int rtc_reg_init(void);
void rtc_osc_init(void);
int rtc_powerkey_init(void);
void rtc_boot_common(void);
static inline s32 rtc_read(u16 addr, u16 *rdata)
{
s32 ret;
ret = pwrap_read(addr, rdata);
if (ret < 0)
rtc_info("pwrap_read fail: ret=%d\n", ret);
return ret;
}
static inline s32 rtc_write(u16 addr, u16 wdata)
{
s32 ret;
ret = pwrap_write(addr, wdata);
if (ret < 0)
rtc_info("pwrap_write fail: ret=%d\n", ret);
return ret;
}
#endif /* SOC_MEDIATEK_RTC_COMMON_H */

40
src/soc/mediatek/common/rtc.c
View File

@ -2,7 +2,6 @@
#include <soc/rtc_common.h>
#include <soc/rtc.h>
#include <soc/pmic_wrap.h>
#include <timer.h>
/* ensure rtc write success */
@ -94,6 +93,30 @@ int rtc_xosc_write(u16 val)
return rtc_write_trigger();
}
/* enable lpd subroutine */
int rtc_lpen(u16 con)
{
con &= ~RTC_CON_LPRST;
rtc_write(RTC_CON, con);
if (!rtc_write_trigger())
return 0;
con |= RTC_CON_LPRST;
rtc_write(RTC_CON, con);
if (!rtc_write_trigger())
return 0;
con &= ~RTC_CON_LPRST;
rtc_write(RTC_CON, con);
if (!rtc_write_trigger())
return 0;
return 1;
}
/* initialize rtc related registers */
int rtc_reg_init(void)
{
@ -129,6 +152,14 @@ int rtc_reg_init(void)
return rtc_write_trigger();
}
/* write powerkeys to enable rtc functions */
int rtc_powerkey_init(void)
{
rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
return rtc_write_trigger();
}
static u8 rtc_check_state(void)
{
u16 con;
@ -164,18 +195,21 @@ void rtc_boot_common(void)
switch (rtc_check_state()) {
case RTC_STATE_REBOOT:
pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD,
0xFFFF, 0);
rtc_read(RTC_BBPU, &bbpu);
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
rtc_write_trigger();
rtc_osc_init();
rtc_info("RTC_STATE_REBOOT\n");
break;
case RTC_STATE_RECOVER:
rtc_init(1);
rtc_info("RTC_STATE_RECOVER\n");
break;
case RTC_STATE_INIT:
default:
if (rtc_init(0))
rtc_init(1);
rtc_info("RTC_STATE_INIT\n");
break;
}

67
src/soc/mediatek/common/rtc_osc_init.c Normal file
View File

@ -0,0 +1,67 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/rtc.h>
#include <soc/rtc_common.h>
/* 32k clock calibration */
static int rtc_eosc_cali(void)
{
u16 diff_left, diff_right, cksel;
u16 val = 0;
u16 middle;
u16 left = RTC_XOSCCALI_START;
u16 right = RTC_XOSCCALI_END;
rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
cksel &= ~PMIC_FQMTR_CKSEL_MASK;
/* select EOSC_32 as fixed clock */
rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K);
rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
rtc_info("PMIC_RG_FQMTR_CKSEL=%#x\n", cksel);
while (left <= right) {
middle = (right + left) / 2;
if (middle == left)
break;
/* select 26M as target clock */
val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0);
if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
break;
if (val > RTC_FQMTR_HIGH_BASE)
right = middle;
else
left = middle;
}
if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
return middle;
val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0);
diff_left = ABS(val - RTC_FQMTR_LOW_BASE);
val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0);
diff_right = ABS(val - RTC_FQMTR_LOW_BASE);
rtc_info("left: %d, middle: %d, right: %d\n", left, middle, right);
if (diff_left < diff_right)
return left;
else
return right;
}
void rtc_osc_init(void)
{
u16 osc32con;
/* enable 32K export */
rtc_gpio_init();
/* calibrate eosc32 for powerdown clock */
rtc_read(RTC_OSC32CON, &osc32con);
rtc_info("osc32con val = %#x\n", osc32con);
osc32con &= ~RTC_XOSCCALI_MASK;
osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK;
rtc_xosc_write(osc32con);
rtc_info("EOSC32 cali val = %#x\n", osc32con);
}

26
src/soc/mediatek/mt8173/include/soc/rtc.h
View File

@ -3,6 +3,7 @@
#ifndef SOC_MEDIATEK_MT8173_RTC_H
#define SOC_MEDIATEK_MT8173_RTC_H
#include <soc/pmic_wrap_common.h>
#include <soc/rtc_common.h>
#include <stdint.h>
#include "mt6391.h"
@ -98,8 +99,29 @@ enum {
};
/* external API */
void rtc_osc_init(void);
int rtc_init(u8 recover);
int rtc_init(int recover);
void rtc_boot(void);
static inline s32 rtc_read(u16 addr, u16 *rdata)
{
s32 ret;
ret = pwrap_read(addr, rdata);
if (ret < 0)
rtc_info("pwrap_read failed: ret=%d\n", ret);
return ret;
}
static inline s32 rtc_write(u16 addr, u16 wdata)
{
s32 ret;
ret = pwrap_write(addr, wdata);
if (ret < 0)
rtc_info("pwrap_write failed: ret=%d\n", ret);
return ret;
}
#endif /* SOC_MEDIATEK_MT8173_RTC_H */

5
src/soc/mediatek/mt8173/rtc.c
View File

@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <delay.h>
#include <soc/rtc_common.h>
#include <soc/rtc.h>
#include <soc/rtc_common.h>
#include <soc/mt6391.h>
#include <soc/pmic_wrap.h>
#include <types.h>
@ -59,7 +59,7 @@ static int rtc_lpd_init(void)
}
/* rtc init check */
int rtc_init(u8 recover)
int rtc_init(int recover)
{
int ret;
@ -84,6 +84,7 @@ int rtc_init(u8 recover)
goto err;
}
/* In recovery mode, we need delay for register setting. */
if (recover)
mdelay(1000);

4
src/soc/mediatek/mt8183/Makefile.inc
View File

@ -37,7 +37,7 @@ romstage-y += ../common/gpio.c gpio.c
romstage-y += ../common/mmu_operations.c mmu_operations.c
romstage-y += ../common/pll.c pll.c
romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c
romstage-y += ../common/rtc.c rtc.c
romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
romstage-y += ../common/i2c.c i2c.c
romstage-y += ../common/timer.c
@ -54,7 +54,7 @@ ramstage-y += ../common/mcu.c
ramstage-y += ../common/mmu_operations.c mmu_operations.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-y += ../common/pmic_wrap.c
ramstage-y += ../common/rtc.c rtc.c
ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
ramstage-y += soc.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += spm.c

28
src/soc/mediatek/mt8183/include/soc/rtc.h
View File

@ -3,6 +3,7 @@
#ifndef SOC_MEDIATEK_MT8183_RTC_H
#define SOC_MEDIATEK_MT8183_RTC_H
#include <soc/pmic_wrap_common.h>
#include <soc/rtc_common.h>
/* RTC registers */
@ -203,9 +204,32 @@ enum {
/* external API */
void rtc_bbpu_power_on(void);
void rtc_osc_init(void);
int rtc_init(u8 recover);
int rtc_init(int recover);
int rtc_gpio_init(void);
void rtc_boot(void);
u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
void mt6358_dcxo_disable_unused(void);
static inline s32 rtc_read(u16 addr, u16 *rdata)
{
s32 ret;
ret = pwrap_read(addr, rdata);
if (ret < 0)
rtc_info("pwrap_read failed: ret=%d\n", ret);
return ret;
}
static inline s32 rtc_write(u16 addr, u16 wdata)
{
s32 ret;
ret = pwrap_write(addr, wdata);
if (ret < 0)
rtc_info("pwrap_write failed: ret=%d\n", ret);
return ret;
}
#endif /* SOC_MEDIATEK_MT8183_RTC_H */

109
src/soc/mediatek/mt8183/rtc.c
View File

@ -2,8 +2,8 @@
#include <delay.h>
#include <halt.h>
#include <soc/rtc_common.h>
#include <soc/rtc.h>
#include <soc/rtc_common.h>
#include <soc/mt6358.h>
#include <soc/pmic_wrap.h>
#include <timer.h>
@ -20,7 +20,7 @@ static int rtc_enable_dcxo(void)
rtc_write_trigger();
mdelay(1);
if (!rtc_writeif_unlock()) { /* Unlock for reload */
if (!rtc_writeif_unlock()) {
rtc_info("rtc_writeif_unlock() failed\n");
return 0;
}
@ -44,7 +44,7 @@ static int rtc_enable_dcxo(void)
}
/* initialize rtc related gpio */
static int rtc_gpio_init(void)
int rtc_gpio_init(void)
{
u16 con;
@ -67,7 +67,7 @@ static int rtc_gpio_init(void)
return rtc_write_trigger();
}
static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
{
u16 bbpu, osc32con;
u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel;
@ -142,93 +142,6 @@ static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
return fqmtr_data;
}
/* 32k clock calibration */
static u16 rtc_eosc_cali(void)
{
u16 middle, diff1, diff2, cksel;
u16 val = 0;
u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END;
rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
cksel &= ~PMIC_FQMTR_CKSEL_MASK;
/* select EOSC_32 as fixed clock */
rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K);
rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
rtc_info("PMIC_RG_FQMTR_CKSEL=0x%x\n", cksel);
while (left <= right) {
middle = (right + left) / 2;
if (middle == left)
break;
/* select 26M as target clock */
val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0);
if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
break;
if (val > RTC_FQMTR_HIGH_BASE)
right = middle;
else
left = middle;
}
if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
return middle;
val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0);
if (val > RTC_FQMTR_LOW_BASE)
diff1 = val - RTC_FQMTR_LOW_BASE;
else
diff1 = RTC_FQMTR_LOW_BASE - val;
val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0);
if (val > RTC_FQMTR_LOW_BASE)
diff2 = val - RTC_FQMTR_LOW_BASE;
else
diff2 = RTC_FQMTR_LOW_BASE - val;
if (diff1 < diff2)
return left;
else
return right;
}
void rtc_osc_init(void)
{
u16 osc32con;
/* enable 32K export */
rtc_gpio_init();
/* Calibrate eosc32 for powerdown clock */
rtc_read(RTC_OSC32CON, &osc32con);
osc32con &= ~RTC_XOSCCALI_MASK;
osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK;
rtc_xosc_write(osc32con);
rtc_info("EOSC32 cali val = 0x%x\n", osc32con);
}
/* enable lpd subroutine */
static int rtc_lpen(u16 con)
{
con &= ~RTC_CON_LPRST;
rtc_write(RTC_CON, con);
if (!rtc_write_trigger())
return 0;
con |= RTC_CON_LPRST;
rtc_write(RTC_CON, con);
if (!rtc_write_trigger())
return 0;
con &= ~RTC_CON_LPRST;
rtc_write(RTC_CON, con);
if (!rtc_write_trigger())
return 0;
return 1;
}
/* low power detect setting */
static int rtc_lpd_init(void)
{
@ -291,16 +204,8 @@ static bool rtc_hw_init(void)
return true;
}
/* write powerkeys to enable rtc functions */
static int rtc_powerkey_init(void)
{
rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
return rtc_write_trigger();
}
/* rtc init check */
int rtc_init(u8 recover)
int rtc_init(int recover)
{
int ret;
@ -320,6 +225,7 @@ int rtc_init(u8 recover)
rtc_osc_init();
/* In recovery mode, we need 20ms delay for register setting. */
if (recover)
mdelay(20);
@ -343,7 +249,8 @@ int rtc_init(u8 recover)
goto err;
}
/* After lpd init, powerkeys need to be written again to enable
/*
* After lpd init, powerkeys need to be written again to enable
* low power detect function.
*/
if (!rtc_powerkey_init()) {

1
src/soc/mediatek/mt8192/Makefile.inc
View File

@ -12,6 +12,7 @@ bootblock-y += ../common/timer.c
bootblock-y += ../common/uart.c
bootblock-y += ../common/wdt.c
bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c
bootblock-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
bootblock-y += mt6315.c
bootblock-y += mt6359p.c

2
src/soc/mediatek/mt8192/bootblock.c
View File

@ -6,6 +6,7 @@
#include <soc/mt6359p.h>
#include <soc/pll.h>
#include <soc/pmif.h>
#include <soc/rtc.h>
#include <soc/wdt.h>
void bootblock_soc_init(void)
@ -16,4 +17,5 @@ void bootblock_soc_init(void)
mtk_pmif_init();
mt6359p_init();
mt6315_init();
rtc_boot();
}

231
src/soc/mediatek/mt8192/include/soc/rtc.h Normal file
View File

@ -0,0 +1,231 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_MEDIATEK_MT8192_RTC_H
#define SOC_MEDIATEK_MT8192_RTC_H
#include <soc/pmif.h>
/* RTC registers */
enum {
RTC_BBPU = 0x0588,
RTC_IRQ_STA = 0x058A,
RTC_IRQ_EN = 0x058C,
RTC_CII_EN = 0x058E,
};
enum {
RTC_TC_SEC = 0x0592,
RTC_TC_MIN = 0x0594,
RTC_TC_HOU = 0x0596,
RTC_TC_DOM = 0x0598,
RTC_TC_DOW = 0x059A,
RTC_TC_MTH = 0x059C,
RTC_TC_YEA = 0x059E,
};
enum {
RTC_AL_SEC = 0x05A0,
RTC_AL_MIN = 0x05A2,
RTC_AL_HOU = 0x05A4,
RTC_AL_DOM = 0x05A6,
RTC_AL_DOW = 0x05A8,
RTC_AL_MTH = 0x05AA,
RTC_AL_YEA = 0x05AC,
RTC_AL_MASK = 0x0590,
};
enum {
RTC_OSC32CON = 0x05AE,
RTC_CON = 0x05C4,
RTC_WRTGR = 0x05C2,
};
enum {
RTC_POWERKEY1 = 0x05B0,
RTC_POWERKEY2 = 0x05B2,
};
enum {
RTC_PDN1 = 0x05B4,
RTC_PDN2 = 0x05B6,
RTC_SPAR0 = 0x05B8,
RTC_SPAR1 = 0x05BA,
RTC_PROT = 0x05BC,
RTC_DIFF = 0x05BE,
RTC_CALI = 0x05C0,
};
enum {
RTC_BBPU_ENABLE_ALARM = 1U << 0,
RTC_BBPU_SPAR_SW = 1U << 1,
RTC_BBPU_RESET_SPAR = 1U << 2,
RTC_BBPU_RESET_ALARM = 1U << 3,
RTC_BBPU_CLRPKY = 1U << 4,
RTC_BBPU_RELOAD = 1U << 5,
RTC_BBPU_CBUSY = 1U << 6,
RTC_CBUSY_TIMEOUT_US = 1000000,
};
enum {
RTC_CON_VBAT_LPSTA_RAW = 1U << 0,
RTC_CON_EOSC32_LPEN = 1U << 1,
RTC_CON_XOSC32_LPEN = 1U << 2,
RTC_CON_LPRST = 1U << 3,
RTC_CON_CDBO = 1U << 4,
RTC_CON_F32KOB = 1U << 5,
RTC_CON_GPO = 1U << 6,
RTC_CON_GOE = 1U << 7,
RTC_CON_GSR = 1U << 8,
RTC_CON_GSMT = 1U << 9,
RTC_CON_GPEN = 1U << 10,
RTC_CON_GPU = 1U << 11,
RTC_CON_GE4 = 1U << 12,
RTC_CON_GE8 = 1U << 13,
RTC_CON_GPI = 1U << 14,
RTC_CON_LPSTA_RAW = 1U << 15,
};
enum {
RTC_XOSCCALI_MASK = 0x1F << 0,
RTC_XOSC32_ENB = 1U << 5,
RTC_EMB_HW_MODE = 0U << 6,
RTC_EMB_K_EOSC32_MODE = 1U << 6,
RTC_EMB_SW_DCXO_MODE = 2U << 6,
RTC_EMB_SW_EOSC32_MODE = 3U << 6,
RTC_EMBCK_SEL_MODE_MASK = 3U << 6,
RTC_EMBCK_SRC_SEL = 1U << 8,
RTC_EMBCK_SEL_OPTION = 1U << 9,
RTC_GPS_CKOUT_EN = 1U << 10,
RTC_EOSC32_VCT_EN = 1U << 11,
RTC_EOSC32_CHOP_EN = 1U << 12,
RTC_GP_OSC32_CON = 2U << 13,
RTC_REG_XOSC32_ENB = 1U << 15,
};
enum {
OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
RTC_EMB_K_EOSC32_MODE,
};
enum {
RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
RTC_LPD_OPT_EOSC_LPD = 1U << 13,
RTC_LPD_OPT_XOSC_LPD = 2U << 13,
RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
RTC_LPD_OPT_MASK = 3U << 13,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_SCK_TOP_CON0 = 0x050C,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C,
};
enum {
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
PMIC_RG_FQMTR_CK_PDN_SHIFT = 11,
};
enum {
PMIC_RG_BANK_FQMTR_RST = 0x522,
};
enum {
PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
};
/* PMIC DCXO Register Definition */
enum {
PMIC_RG_DCXO_CW00 = 0x0788,
PMIC_RG_DCXO_CW00_SET = 0x078A,
PMIC_RG_DCXO_CW00_CLR = 0x078C,
PMIC_RG_DCXO_CW02 = 0x0790,
PMIC_RG_DCXO_CW08 = 0x079C,
PMIC_RG_DCXO_CW09 = 0x079E,
PMIC_RG_DCXO_CW09_SET = 0x07A0,
PMIC_RG_DCXO_CW09_CLR = 0x07A2,
PMIC_RG_DCXO_CW12 = 0x07A8,
};
/* PMIC Frequency Meter Definition */
enum {
PMIC_RG_FQMTR_CKSEL = 0x0118,
PMIC_RG_FQMTR_RST = 0x013A,
PMIC_RG_FQMTR_CON0 = 0x0546,
PMIC_RG_FQMTR_WINSET = 0x0548,
PMIC_RG_FQMTR_DATA = 0x054A,
FQMTR_TIMEOUT_US = 8000,
};
enum {
PMIC_FQMTR_FIX_CLK_26M = 0U << 0,
PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0,
PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0,
PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0,
PMIC_FQMTR_FIX_CLK_DCXO1M_CK = 4U << 0,
PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0,
PMIC_FQMTR_FIX_CLK_PMU_32K = 6U << 0,
PMIC_FQMTR_CKSEL_MASK = 7U << 0,
};
enum {
PMIC_FQMTR_RST_SHIFT = 8,
};
enum {
PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0,
PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0,
PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0,
PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0,
PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0,
PMIC_FQMTR_CON0_TEST_CK = 6U << 0,
PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0,
PMIC_FQMTR_CON0_BUSY = 1U << 3,
PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4,
PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15,
};
enum {
RTC_FQMTR_LOW_BASE = 794 - 2,
RTC_FQMTR_HIGH_BASE = 794 + 2,
};
enum {
RTC_XOSCCALI_START = 0x00,
RTC_XOSCCALI_END = 0x1f,
};
enum {
RTC_TC_MTH_MASK = 0xf,
};
enum {
RTC_K_EOSC_RSV_0 = 1 << 8,
RTC_K_EOSC_RSV_1 = 1 << 9,
RTC_K_EOSC_RSV_2 = 1 << 10,
};
void rtc_read(u16 addr, u16 *rdata);
void rtc_write(u16 addr, u16 wdata);
void rtc_bbpu_power_on(void);
int rtc_init(int recover);
int rtc_gpio_init(void);
void rtc_boot(void);
u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
void mt6359_dcxo_disable_unused(void);
#endif /* SOC_MEDIATEK_MT8192_RTC_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <delay.h>
#include <halt.h>
#include <soc/mt6359p.h>
#include <soc/pmif.h>
#include <soc/rtc.h>
#include <soc/rtc_common.h>
#include <timer.h>
#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8))
static struct pmif *pmif_arb = NULL;
void rtc_read(u16 addr, u16 *rdata)
{
u32 data;
if (pmif_arb == NULL)
pmif_arb = get_pmif_controller(PMIF_SPI, 0);
pmif_arb->read(pmif_arb, 0, (u32)addr, &data);
*rdata = (u16)data;
}
void rtc_write(u16 addr, u16 wdata)
{
if (pmif_arb == NULL)
pmif_arb = get_pmif_controller(PMIF_SPI, 0);
pmif_arb->write(pmif_arb, 0, (unsigned int)addr, (unsigned int)wdata);
}
static void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift)
{
u16 old, new;
rtc_read(reg, &old);
new = old & ~(mask << shift);
new |= (val << shift);
rtc_write(reg, new);
}
/* initialize rtc setting of using dcxo clock */
static int rtc_enable_dcxo(void)
{
if (!rtc_writeif_unlock()) {
rtc_info("rtc_writeif_unlock() failed\n");
return 0;
}
u16 bbpu, con, osc32con, sec;
rtc_read(RTC_BBPU, &bbpu);
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
rtc_write_trigger();
rtc_read(RTC_OSC32CON, &osc32con);
osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK);
osc32con |= (OSC32CON_ANALOG_SETTING | RTC_REG_XOSC32_ENB);
if (!rtc_xosc_write(osc32con)) {
rtc_info("rtc_xosc_write() failed\n");
return 0;
}
rtc_read(RTC_CON, &con);
rtc_read(RTC_OSC32CON, &osc32con);
rtc_read(RTC_AL_SEC, &sec);
rtc_info("con=%#x, osc32con=%#x, sec=%#x\n", con, osc32con, sec);
return 1;
}
/* initialize rtc related gpio */
int rtc_gpio_init(void)
{
u16 con;
/* GPI mode and pull down */
rtc_read(RTC_CON, &con);
con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN
| RTC_CON_XOSC32_LPEN);
con |= (RTC_CON_GPEN | RTC_CON_GOE);
con &= ~(RTC_CON_F32KOB);
con &= ~RTC_CON_GPU;
rtc_write(RTC_CON, con);
return rtc_write_trigger();
}
u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
{
u16 bbpu, osc32con;
u16 fqmtr_busy, fqmtr_data, fqmtr_tcksel;
struct stopwatch sw;
if (val) {
rtc_read(RTC_BBPU, &bbpu);
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
rtc_write_trigger();
rtc_read(RTC_OSC32CON, &osc32con);
rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) |
(val & RTC_XOSCCALI_MASK));
}
/* RG_BANK_FQMTR_RST=1, reset FQMTR*/
rtc_write_field(PMIC_RG_BANK_FQMTR_RST, 1, 1,
PMIC_RG_BANK_FQMTR_RST_SHIFT);
udelay(20);
/* RG_BANK_FQMTR_RST=0, release FQMTR*/
rtc_write_field(PMIC_RG_BANK_FQMTR_RST, 0, 1,
PMIC_RG_BANK_FQMTR_RST_SHIFT);
/* enable FQMTR clock */
rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
PMIC_RG_FQMTR_CK_PDN_SHIFT);
rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
rtc_write_field(PMIC_RG_FQMTR_CON0, 1, 1,
PMIC_RG_FQMTR_DCXO26M_EN_SHIFT);
/* set frequency meter window value (0=1X32K(fixed clock)) */
rtc_write(PMIC_RG_FQMTR_WINSET, window_size);
/* enable 26M and set test clock source */
rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src);
/* enable 26M -> delay 100us -> enable FQMTR */
mdelay(1);
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
/* enable FQMTR */
rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN);
mdelay(1);
stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US);
/* FQMTR read until ready */
do {
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
if (stopwatch_expired(&sw)) {
rtc_info("get frequency time out!\n");
return 0;
}
} while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);
/* read data should be closed to 26M/32k = 794 */
rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
/* disable FQMTR */
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN);
/* disable FQMTR -> delay 100us -> disable 26M */
mdelay(1);
/* disable 26M */
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
rtc_write(PMIC_RG_FQMTR_CON0,
fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN);
rtc_info("input=%d, output=%d\n", val, fqmtr_data);
/* disable FQMTR clock */
rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
PMIC_RG_FQMTR_CK_PDN_SHIFT);
rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
return fqmtr_data;
}
/* low power detect setting */
static int rtc_lpd_init(void)
{
u16 con, sec;
/* enable both XOSC & EOSC LPD */
rtc_read(RTC_AL_SEC, &sec);
sec &= ~RTC_LPD_OPT_F32K_CK_ALIVE;
rtc_write(RTC_AL_SEC, sec);
if (!rtc_write_trigger())
return 0;
/* init XOSC32 to detect 32k clock stop */
rtc_read(RTC_CON, &con);
con |= RTC_CON_XOSC32_LPEN;
if (!rtc_lpen(con))
return 0;
/* init EOSC32 to detect rtc low power */
rtc_read(RTC_CON, &con);
con |= RTC_CON_EOSC32_LPEN;
if (!rtc_lpen(con))
return 0;
rtc_read(RTC_CON, &con);
rtc_info("check RTC_CON_LPSTA_RAW after LP init: %#x\n", con);
return 1;
}
static bool rtc_hw_init(void)
{
u16 bbpu;
rtc_read(RTC_BBPU, &bbpu);
bbpu |= RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR;
rtc_write(RTC_BBPU, bbpu & (~RTC_BBPU_SPAR_SW));
rtc_write_trigger();
udelay(500);
rtc_read(RTC_BBPU, &bbpu);
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
rtc_write_trigger();
rtc_read(RTC_BBPU, &bbpu);
if (bbpu & RTC_BBPU_RESET_ALARM || bbpu & RTC_BBPU_RESET_SPAR) {
rtc_info("timeout\n");
return false;
}
return true;
}
/* rtc init check */
int rtc_init(int recover)
{
int ret;
u16 year;
rtc_info("recovery: %d\n", recover);
/* write powerkeys to enable rtc functions */
if (!rtc_powerkey_init()) {
ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
goto err;
}
/* write interface unlock need to be set after powerkey match */
if (!rtc_writeif_unlock()) {
ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
goto err;
}
rtc_osc_init();
/* In recovery mode, we need 20ms delay for register setting. */
if (recover)
mdelay(20);
if (!rtc_gpio_init()) {
ret = -RTC_STATUS_GPIO_INIT_FAIL;
goto err;
}
if (!rtc_hw_init()) {
ret = -RTC_STATUS_HW_INIT_FAIL;
goto err;
}
if (!rtc_reg_init()) {
ret = -RTC_STATUS_REG_INIT_FAIL;
goto err;
}
/* solution1 for EOSC cali*/
rtc_read(RTC_AL_YEA, &year);
rtc_write(RTC_AL_YEA, (year | RTC_K_EOSC_RSV_0) & (~RTC_K_EOSC_RSV_1)
& (~RTC_K_EOSC_RSV_2));
rtc_write_trigger();
if (!rtc_lpd_init()) {
ret = -RTC_STATUS_LPD_INIT_FAIL;
goto err;
}
/*
* After lpd init, powerkeys need to be written again to enable
* low power detect function.
*/
if (!rtc_powerkey_init()) {
ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
goto err;
}
return RTC_STATUS_OK;
err:
rtc_info("init failed: ret=%d\n", ret);
return ret;
}
/* enable rtc bbpu */
void rtc_bbpu_power_on(void)
{
u16 bbpu;
int ret;
/* pull powerhold high, control by pmic */
rtc_write_field(PMIC_PWRHOLD, 1, 0x1, 0);
bbpu = RTC_BBPU_KEY | RTC_BBPU_ENABLE_ALARM;
rtc_write(RTC_BBPU, bbpu);
ret = rtc_write_trigger();
rtc_info("rtc_write_trigger=%d\n", ret);
rtc_read(RTC_BBPU, &bbpu);
rtc_info("done BBPU=%#x\n", bbpu);
}
void poweroff(void)
{
u16 bbpu;
if (!rtc_writeif_unlock())
rtc_info("rtc_writeif_unlock() failed\n");
/* pull PWRBB low */
bbpu = RTC_BBPU_KEY | RTC_BBPU_ENABLE_ALARM;
rtc_write(RTC_BBPU, bbpu);
rtc_write_field(PMIC_PWRHOLD, 0, 0x1, 0);
halt();
}
static void dcxo_init(void)
{
u16 tmp;
rtc_read(PMIC_RG_DCXO_CW00, &tmp);
rtc_info("CW00,%#x:%#x\n", PMIC_RG_DCXO_CW00, tmp);
rtc_read(PMIC_RG_DCXO_CW09, &tmp);
rtc_info("CW09,%#x:%#x\n", PMIC_RG_DCXO_CW09, tmp);
rtc_read(PMIC_RG_DCXO_CW08, &tmp);
rtc_info("CW08,%#x:%#x\n", PMIC_RG_DCXO_CW08, tmp);
/* 26M enable control */
/* enable clock buffer XO_SOC */
rtc_write_field(PMIC_RG_DCXO_CW00, 0x4005, 0xFFFF, 0);
rtc_read(PMIC_RG_DCXO_CW00, &tmp);
rtc_info("CW0,%#x:%#x\n", PMIC_RG_DCXO_CW00, tmp);
rtc_write_field(PMIC_RG_DCXO_CW09_CLR, 0x3f, 0x3f, 9);
rtc_read(PMIC_RG_DCXO_CW09, &tmp);
rtc_info("PMIC_RG_DCXO_CW09,%#x:%#x\n", PMIC_RG_DCXO_CW09, tmp);
/* mode and buffer controlled by srclken0 */
rtc_write_field(PMIC_RG_DCXO_CW08, 0x1, 0x1, 2);
rtc_read(PMIC_RG_DCXO_CW08, &tmp);
rtc_info("PMIC_RG_DCXO_CW08,%#x:%#x\n", PMIC_RG_DCXO_CW08, tmp);
}
void mt6359_dcxo_disable_unused(void)
{
/* disable HW BBLPM arbiter */
rtc_write_field(PMIC_RG_DCXO_CW12, 0x2, 0x3, 0);
}
/* the rtc boot flow entry */
void rtc_boot(void)
{
u16 tmp;
/* dcxo clock init settings */
dcxo_init();
/* dcxo 32k init settings */
rtc_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
rtc_read(PMIC_RG_SCK_TOP_CON0, &tmp);
rtc_info("PMIC_RG_SCK_TOP_CON0,%#x:%#x\n", PMIC_RG_SCK_TOP_CON0, tmp);
rtc_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
rtc_read(PMIC_RG_SCK_TOP_CON0, &tmp);
rtc_info("PMIC_RG_SCK_TOP_CON0,%#x:%#x\n", PMIC_RG_SCK_TOP_CON0, tmp);
/* use dcxo 32K clock */
if (!rtc_enable_dcxo())
rtc_info("rtc_enable_dcxo() failed\n");
rtc_boot_common();
rtc_bbpu_power_on();
}