soc/intel/cannonlake: Move `gpi_clear_int_cfg()` call

To allow unifying bootblock.c in follow-ups, move a function call.

Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/cannonlake/bootblock/bootblock.c

@@ -61,11 +61,6 @@ void bootblock_soc_early_init(void)
 
 void bootblock_soc_init(void)
 {
-	/*
-	 * Clear the GPI interrupt status and enable registers. These
-	 * registers do not get reset to default state when booting from S5.
-	 */
-	gpi_clear_int_cfg();
 	report_platform_info();
 	bootblock_pch_init();
 

src/soc/intel/cannonlake/bootblock/pch.c

@@ -6,6 +6,7 @@
 #include <device/pci_ops.h>
 #include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/p2sb.h>
@@ -131,6 +132,12 @@ void pch_early_iorange_init(void)
 
 void bootblock_pch_init(void)
 {
+	/*
+	 * Clear the GPI interrupt status and enable registers. These
+	 * registers do not get reset to default state when booting from S5.
+	 */
+	gpi_clear_int_cfg();
+
 	/*
 	 * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
 	 * GPE0_STS, GPE0_EN registers.