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Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration" 

This reverts commit 214c719eed.
CB:45857 overrides the GPIO PM configuration if Cr50 does not support
long interrupt pulse width. More recent Cr50 Firmware versions support
long pulse width and hence the GPIO PM can take the default
configuration.

BUG=None
TEST=Build and boot Drawlat to OS. Ensured that 200 iterations of
suspend/resume sequence, warm and cold reboot cycles each are
successful.

Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2020-10-22 00:23:32 -06:00 committed by Patrick Georgi
parent 7c80de6328
commit b11b731e80
2 changed files with 0 additions and 52 deletions
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45
src/mainboard/google/dedede/acpi/mainboard.asl
View File

@ -1,45 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <intelblocks/gpio.h>
#include <soc/gpio_soc_defs.h>
Method (PGPM, 1, Serialized)
{
For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
{
\_SB.PCI0.CGPM (Local0, Arg0)
}
}
/*
* Method called from _PTS prior to system sleep state entry
* Enables dynamic clock gating for all 5 GPIO communities
*/
Method (MPTS, 1, Serialized)
{
PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
}
/*
* Method called from _WAK prior to system sleep state wakeup
* Disables dynamic clock gating for all 5 GPIO communities
*/
Method (MWAK, 1, Serialized)
{
PGPM (0)
}
/*
* S0ix Entry/Exit Notifications
* Called from \_SB.LPID._DSM
*/
Method (MS0X, 1, Serialized)
{
If (Arg0 == 1) {
/* S0ix Entry */
PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
} Else {
/* S0ix Exit */
PGPM (0)
}
}

7
src/mainboard/google/dedede/dsdt.asl
View File

@ -27,9 +27,6 @@ DefinitionBlock(
#include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/jasperlake/acpi/southbridge.asl> #include <soc/intel/jasperlake/acpi/southbridge.asl>
} }
/* Mainboard hooks */
#include "acpi/mainboard.asl"
} }
#if CONFIG(VARIANT_HAS_CAMERA_ACPI) #if CONFIG(VARIANT_HAS_CAMERA_ACPI)
@ -37,10 +34,6 @@ DefinitionBlock(
#include <variant/acpi/camera.asl> #include <variant/acpi/camera.asl>
#endif #endif
/* Include Low power idle table for a short term workaround to enable
S0ix. Once cr50 pulse width is fixed, this can be removed. */
#include <soc/intel/common/acpi/lpit.asl>
/* Chrome OS specific */ /* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>