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mb/google/brya/var/primus: Disable autonomous GPIO power management 

Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:201054849
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.

Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Casper Chang 2021-11-10 09:52:18 +08:00 committed by Paul Fagerburg
parent 09a66ace7e
commit b139e6b2a3
1 changed files with 10 additions and 1 deletions
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11
src/mainboard/google/brya/variants/primus/overridetree.cb
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@ -22,7 +22,16 @@ fw_config
end end
chip soc/intel/alderlake chip soc/intel/alderlake
# This disabled autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses; need to clarify
# the minimum PCH IRQ pulse width with Intel, b/180111628
register "gpio_override_pm" = "1"
register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_1]" = "0"
register "gpio_pm[COMM_2]" = "0"
register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0"
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
register "MaxDramSpeed" = "3733" register "MaxDramSpeed" = "3733"