Revert "soc/intel: Refactor do_global_reset() function"
This reverts commit 77cc3267fc
.
Reason for revert: Breaks quark and also needs breaking down into multiple CLs as commented by Nico on CB:45541
Change-Id: Idf4ca74158df15483856754ee24cc4472a8e09b0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
parent
5bd4adf542
commit
b13bd1efcf
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@ -1,8 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/pmclib.h>
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#include <fsp/util.h>
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#include <fsp/util.h>
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#include <soc/intel/common/reset.h>
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#include <soc/intel/common/reset.h>
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#include <soc/pci_devs.h>
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void do_global_reset(void)
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{
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/* Ask CSE to do the global reset */
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if (cse_request_global_reset())
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return;
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/* global reset if CSE fail to reset */
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pmc_global_reset_enable(1);
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do_full_reset();
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}
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void chipset_handle_reset(uint32_t status)
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void chipset_handle_reset(uint32_t status)
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{
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{
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@ -99,6 +99,7 @@ config CPU_SPECIFIC_OPTIONS
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select UDK_2015_BINDING if !SOC_INTEL_GEMINILAKE
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select UDK_2015_BINDING if !SOC_INTEL_GEMINILAKE
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select UDK_2017_BINDING if SOC_INTEL_GEMINILAKE
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select UDK_2017_BINDING if SOC_INTEL_GEMINILAKE
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_RESET
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select HAVE_CF9_RESET_PREPARE
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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select HAVE_FSP_GOP
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select HAVE_FSP_GOP
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select HAVE_FSP_LOGO_SUPPORT
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select HAVE_FSP_LOGO_SUPPORT
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@ -12,6 +12,7 @@ subdirs-y += ../../../cpu/x86/cache
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/bootblock.c
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bootblock-$(CONFIG_FSP_CAR) += fspcar.c
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bootblock-$(CONFIG_FSP_CAR) += fspcar.c
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bootblock-y += car.c
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bootblock-y += car.c
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bootblock-y += heci.c
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bootblock-y += gspi.c
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bootblock-y += gspi.c
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bootblock-y += i2c.c
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bootblock-y += i2c.c
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bootblock-y += lpc.c
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bootblock-y += lpc.c
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@ -25,6 +26,7 @@ romstage-y += ../../../cpu/intel/car/romstage.c
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romstage-y += romstage.c
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romstage-y += romstage.c
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romstage-y += report_platform.c
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romstage-y += report_platform.c
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romstage-y += gspi.c
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romstage-y += gspi.c
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romstage-y += heci.c
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romstage-y += i2c.c
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romstage-y += i2c.c
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romstage-y += uart.c
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romstage-y += uart.c
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romstage-y += meminit.c
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romstage-y += meminit.c
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@ -54,6 +56,7 @@ ramstage-y += cse.c
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ramstage-y += elog.c
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ramstage-y += elog.c
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ramstage-y += graphics.c
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ramstage-y += graphics.c
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ramstage-y += gspi.c
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ramstage-y += gspi.c
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ramstage-y += heci.c
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ramstage-y += i2c.c
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ramstage-y += i2c.c
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ramstage-y += lpc.c
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ramstage-y += lpc.c
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ramstage-y += mmap_boot.c
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ramstage-y += mmap_boot.c
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@ -72,6 +75,7 @@ ramstage-y += xhci.c
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postcar-y += mmap_boot.c
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postcar-y += mmap_boot.c
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postcar-y += spi.c
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postcar-y += spi.c
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postcar-y += i2c.c
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postcar-y += i2c.c
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postcar-y += heci.c
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postcar-y += reset.c
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postcar-y += reset.c
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postcar-y += uart.c
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postcar-y += uart.c
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postcar-y += gspi.c
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postcar-y += gspi.c
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@ -79,6 +83,7 @@ postcar-y += gspi.c
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verstage-y += car.c
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verstage-y += car.c
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verstage-y += i2c.c
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verstage-y += i2c.c
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verstage-y += gspi.c
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verstage-y += gspi.c
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verstage-y += heci.c
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verstage-y += mmap_boot.c
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verstage-y += mmap_boot.c
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verstage-y += uart.c
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verstage-y += uart.c
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verstage-y += pmutil.c
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verstage-y += pmutil.c
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@ -0,0 +1,22 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <soc/heci.h>
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#include <soc/pci_devs.h>
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uint32_t heci_fw_sts(void)
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{
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return pci_read_config32(PCH_DEV_CSE, REG_SEC_FW_STS0);
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}
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bool heci_cse_normal(void)
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{
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return ((heci_fw_sts() & MASK_SEC_STATUS) == SEC_STATE_NORMAL);
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}
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bool heci_cse_done(void)
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{
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return (!!(heci_fw_sts() & MASK_SEC_FIRMWARE_COMPLETE));
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}
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@ -5,6 +5,29 @@
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#include <stdint.h>
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#include <stdint.h>
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enum sec_status {
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SEC_STATE_RESET = 0,
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SEC_STATE_INIT,
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SEC_STATE_RECOVERY,
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SEC_STATE_UNKNOWN0,
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SEC_STATE_UNKNOWN1,
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SEC_STATE_NORMAL,
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SEC_STATE_DISABLE_WAIT,
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SEC_STATE_TRANSITION,
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SEC_STATE_INVALID_CPU
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};
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#define REG_SEC_FW_STS0 0x40
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#define MASK_SEC_FIRMWARE_COMPLETE (1 << 9)
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#define MASK_SEC_STATUS 0xf
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/* Read Firmware Status register */
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uint32_t heci_fw_sts(void);
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/* Returns true if CSE is in normal status */
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bool heci_cse_normal(void);
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/* Returns true if CSE is done with whatever it was doing */
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bool heci_cse_done(void);
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/* Dump CSE state and lockdown HECI1 interface using P2SB message. */
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/* Dump CSE state and lockdown HECI1 interface using P2SB message. */
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void heci_cse_lockdown(void);
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void heci_cse_lockdown(void);
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@ -1,8 +1,52 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <delay.h>
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#include <fsp/util.h>
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#include <fsp/util.h>
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#include <intelblocks/pmclib.h>
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#include <soc/heci.h>
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#include <soc/intel/common/reset.h>
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#include <soc/intel/common/reset.h>
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#include <soc/pm.h>
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#include <timer.h>
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#define CSE_WAIT_MAX_MS 1000
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void do_global_reset(void)
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{
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pmc_global_reset_enable(1);
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do_full_reset();
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}
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void cf9_reset_prepare(void)
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{
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struct stopwatch sw;
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/*
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* If CSE state is something else than 'normal', it is probably in some
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* recovery state. In this case there is no point in waiting for it to
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* get ready so we cross fingers and reset.
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*/
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if (!heci_cse_normal()) {
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printk(BIOS_DEBUG, "CSE is not in normal state, resetting\n");
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return;
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}
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/* Reset if CSE is ready */
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if (heci_cse_done())
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return;
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printk(BIOS_SPEW, "CSE is not yet ready, waiting\n");
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stopwatch_init_msecs_expire(&sw, CSE_WAIT_MAX_MS);
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while (!heci_cse_done()) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_SPEW, "CSE timed out. Resetting\n");
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return;
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}
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mdelay(1);
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}
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printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw));
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}
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void chipset_handle_reset(uint32_t status)
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void chipset_handle_reset(uint32_t status)
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{
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{
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@ -1,8 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/pmclib.h>
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#include <fsp/util.h>
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#include <fsp/util.h>
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#include <soc/intel/common/reset.h>
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#include <soc/intel/common/reset.h>
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#include <soc/pci_devs.h>
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void do_global_reset(void)
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{
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/* Ask CSE to do the global reset */
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if (cse_request_global_reset())
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return;
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/* global reset if CSE fail to reset */
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pmc_global_reset_enable(1);
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do_full_reset();
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}
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void chipset_handle_reset(uint32_t status)
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void chipset_handle_reset(uint32_t status)
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{
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{
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@ -384,7 +384,7 @@ static bool cse_set_and_boot_from_next_bp(enum boot_partition_id bp)
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cse_board_reset();
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cse_board_reset();
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/* If board does not perform the reset, then perform global_reset */
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/* If board does not perform the reset, then perform global_reset */
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global_reset();
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do_global_reset();
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die("cse_lite: Failed to reset the system\n");
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die("cse_lite: Failed to reset the system\n");
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@ -4,35 +4,16 @@
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#include <cf9_reset.h>
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <halt.h>
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#include <halt.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/pmclib.h>
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#include <reset.h>
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#include <reset.h>
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#include "reset.h"
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#include "reset.h"
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static void force_global_reset(void)
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{
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/* Ask CSE to do the global reset */
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if (CONFIG(SOC_INTEL_COMMON_BLOCK_CSE))
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if (cse_request_global_reset())
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return;
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/*
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* If ME is unable to reset platform then enable the PMC CF9GR register [B0:D31:F2
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* register offset 0xAC bit 20] and force a global reset by writing 0x06 or 0x0E.
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*/
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if (CONFIG(SOC_INTEL_COMMON_BLOCK_PMC))
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pmc_global_reset_enable(true);
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/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port to global reset platform */
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do_full_reset();
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}
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void global_reset(void)
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void global_reset(void)
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{
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{
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printk(BIOS_INFO, "%s() called!\n", __func__);
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printk(BIOS_INFO, "%s() called!\n", __func__);
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cf9_reset_prepare();
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cf9_reset_prepare();
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dcache_clean_all();
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dcache_clean_all();
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force_global_reset();
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do_global_reset();
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halt();
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halt();
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}
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}
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@ -3,7 +3,14 @@
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#ifndef _INTEL_COMMON_RESET_H_
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#ifndef _INTEL_COMMON_RESET_H_
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#define _INTEL_COMMON_RESET_H_
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#define _INTEL_COMMON_RESET_H_
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/* Prepare for reset, run force_global_reset(), halt. */
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/*
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* Implement SoC specific global reset (i.e. a reset of both host and
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* ME partitions). Usually the ME is asked to perform the reset first.
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* If that doesn't work out, fall back to a manual global reset.
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*/
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void do_global_reset(void);
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/* Prepare for reset, run do_global_reset(), halt. */
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__noreturn void global_reset(void);
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__noreturn void global_reset(void);
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#endif /* _INTEL_COMMON_RESET_H_ */
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#endif /* _INTEL_COMMON_RESET_H_ */
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@ -1,8 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <fsp/util.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/pmclib.h>
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#include <soc/intel/common/reset.h>
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#include <soc/intel/common/reset.h>
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#include <soc/pci_devs.h>
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void do_global_reset(void)
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{
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/* Ask CSE to do the global reset */
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if (cse_request_global_reset())
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return;
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/* global reset if CSE fail to reset */
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pmc_global_reset_enable(1);
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do_full_reset();
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}
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void chipset_handle_reset(uint32_t status)
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void chipset_handle_reset(uint32_t status)
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{
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{
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@ -1,8 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/pmclib.h>
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#include <fsp/util.h>
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#include <fsp/util.h>
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#include <soc/intel/common/reset.h>
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#include <soc/intel/common/reset.h>
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#include <soc/pci_devs.h>
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void do_global_reset(void)
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{
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/* Ask CSE to do the global reset */
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if (cse_request_global_reset())
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return;
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/* global reset if CSE fail to reset */
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pmc_global_reset_enable(1);
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do_full_reset();
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}
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void chipset_handle_reset(uint32_t status)
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void chipset_handle_reset(uint32_t status)
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{
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{
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@ -1,8 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/pmclib.h>
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#include <fsp/util.h>
|
#include <fsp/util.h>
|
||||||
#include <soc/intel/common/reset.h>
|
#include <soc/intel/common/reset.h>
|
||||||
|
#include <soc/pci_devs.h>
|
||||||
|
|
||||||
|
void do_global_reset(void)
|
||||||
|
{
|
||||||
|
/* Ask CSE to do the global reset */
|
||||||
|
if (cse_request_global_reset())
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* global reset if CSE fail to reset */
|
||||||
|
pmc_global_reset_enable(1);
|
||||||
|
do_full_reset();
|
||||||
|
}
|
||||||
|
|
||||||
void chipset_handle_reset(uint32_t status)
|
void chipset_handle_reset(uint32_t status)
|
||||||
{
|
{
|
||||||
|
|
|
@ -178,5 +178,6 @@ union me_hfsts6 {
|
||||||
};
|
};
|
||||||
|
|
||||||
void intel_me_status(void);
|
void intel_me_status(void);
|
||||||
|
int send_global_reset(void);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -338,6 +338,25 @@ void intel_me_status(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int send_global_reset(void)
|
||||||
|
{
|
||||||
|
int status = -1;
|
||||||
|
union me_hfsts1 hfs1;
|
||||||
|
|
||||||
|
if (!is_cse_enabled())
|
||||||
|
goto ret;
|
||||||
|
|
||||||
|
/* Check ME operating mode */
|
||||||
|
hfs1.data = me_read_config32(PCI_ME_HFSTS1);
|
||||||
|
if (hfs1.fields.operation_mode)
|
||||||
|
goto ret;
|
||||||
|
|
||||||
|
/* ME should be in Normal Mode for this command */
|
||||||
|
status = cse_request_global_reset();
|
||||||
|
ret:
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This can't be put in intel_me_status because by the time control
|
* This can't be put in intel_me_status because by the time control
|
||||||
* reaches there, ME doesn't respond to GET_FW_VERSION command.
|
* reaches there, ME doesn't respond to GET_FW_VERSION command.
|
||||||
|
|
|
@ -1,8 +1,35 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
|
||||||
|
#include <cf9_reset.h>
|
||||||
#include <console/console.h>
|
#include <console/console.h>
|
||||||
#include <fsp/util.h>
|
#include <fsp/util.h>
|
||||||
|
#include <intelblocks/pmclib.h>
|
||||||
#include <soc/intel/common/reset.h>
|
#include <soc/intel/common/reset.h>
|
||||||
|
#include <soc/me.h>
|
||||||
|
#include <soc/pm.h>
|
||||||
|
|
||||||
|
static void do_force_global_reset(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* BIOS should ensure it does a global reset
|
||||||
|
* to reset both host and Intel ME by setting
|
||||||
|
* PCH PMC [B0:D31:F2 register offset 0xAC bit 20]
|
||||||
|
*/
|
||||||
|
pmc_global_reset_enable(true);
|
||||||
|
|
||||||
|
/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
|
||||||
|
* to global reset platform */
|
||||||
|
do_full_reset();
|
||||||
|
}
|
||||||
|
|
||||||
|
void do_global_reset(void)
|
||||||
|
{
|
||||||
|
if (!send_global_reset()) {
|
||||||
|
/* If ME unable to reset platform then
|
||||||
|
* force global reset using PMC CF9GR register*/
|
||||||
|
do_force_global_reset();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
void chipset_handle_reset(uint32_t status)
|
void chipset_handle_reset(uint32_t status)
|
||||||
{
|
{
|
||||||
|
|
|
@ -1,8 +1,23 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
|
||||||
|
#include <cf9_reset.h>
|
||||||
#include <console/console.h>
|
#include <console/console.h>
|
||||||
|
#include <intelblocks/cse.h>
|
||||||
|
#include <intelblocks/pmclib.h>
|
||||||
#include <fsp/util.h>
|
#include <fsp/util.h>
|
||||||
#include <soc/intel/common/reset.h>
|
#include <soc/intel/common/reset.h>
|
||||||
|
#include <soc/pci_devs.h>
|
||||||
|
|
||||||
|
void do_global_reset(void)
|
||||||
|
{
|
||||||
|
/* Ask CSE to do the global reset */
|
||||||
|
if (cse_request_global_reset())
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* global reset if CSE fail to reset */
|
||||||
|
pmc_global_reset_enable(1);
|
||||||
|
do_full_reset();
|
||||||
|
}
|
||||||
|
|
||||||
void chipset_handle_reset(uint32_t status)
|
void chipset_handle_reset(uint32_t status)
|
||||||
{
|
{
|
||||||
|
|
Loading…
Reference in New Issue