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soc/intel/apollolake: Enable CACHE_MRC_SETTINGS 

This enables CACHE_MRC_SETTINGS by default as well selects
timer configuration.

Change-Id: I0248001892ef763c39097848b5adc8c1befed1f0
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14252
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Hannah Williams 2016-03-14 17:38:51 -07:00 committed by Martin Roth
parent 064a50160a
commit b13d454f35
2 changed files with 7 additions and 2 deletions
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8
src/soc/intel/apollolake/Kconfig
View File

@ -35,8 +35,8 @@ config CPU_SPECIFIC_OPTIONS
select SPI_FLASH select SPI_FLASH
select UDELAY_TSC select UDELAY_TSC
select TSC_CONSTANT_RATE select TSC_CONSTANT_RATE
select UDELAY_TSC select TSC_MONOTONIC_TIMER
select TSC_CONSTANT_RATE select HAVE_MONOTONIC_TIMER
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
config MMCONF_BASE_ADDRESS config MMCONF_BASE_ADDRESS
@ -100,4 +100,8 @@ config ROMSTAGE_ADDR
help help
The base address (in CAR) where romstage should be linked The base address (in CAR) where romstage should be linked
config CACHE_MRC_SETTINGS
bool
default y
endif endif

1
src/soc/intel/apollolake/Makefile.inc
View File

@ -44,6 +44,7 @@ postcar-y += exit_car.S
postcar-y += memmap.c postcar-y += memmap.c
postcar-y += mmap_boot.c postcar-y += mmap_boot.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
postcar-y += tsc_freq.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include