mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers
This explicitly enables TCSS xHCI, PCIe root ports and DMA controllers from TGL RVP platform devicetree setting. BUG=🅱️146624360 TEST=Built and booted on TGL RVP. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/41386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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@ -109,13 +109,14 @@ chip soc/intel/tigerlake
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[PchSerialIoIndexUART2] = PchSerialIoPci,
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[PchSerialIoIndexUART2] = PchSerialIoPci,
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}"
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}"
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# TCSS USB3
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register "TcssXhciEn" = "1"
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register "TcssAuxOri" = "0"
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# D3Hot and D3Cold for TCSS
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# D3Hot and D3Cold for TCSS
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register "TcssD3HotEnable" = "1"
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register "TcssD3HotEnable" = "1"
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register "TcssD3ColdEnable" = "1"
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register "TcssD3ColdEnable" = "1"
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# TCSS USB3
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register "TcssAuxOri" = "0"
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#HD Audio
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#HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaDspEnable" = "1"
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register "PchHdaAudioLinkHdaEnable" = "0"
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register "PchHdaAudioLinkHdaEnable" = "0"
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@ -153,17 +154,17 @@ chip soc/intel/tigerlake
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device pci 04.0 on end # DPTF 0x9A03
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device pci 04.0 on end # DPTF 0x9A03
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device pci 05.0 on end # IPU 0x9A19
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device pci 05.0 on end # IPU 0x9A19
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device pci 06.0 on end # PEG60 0x9A09
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device pci 06.0 on end # PEG60 0x9A09
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device pci 07.0 off end # TBT_PCIe0 0x9A23
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device pci 07.0 on end # TBT_PCIe0 0x9A23
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device pci 07.1 off end # TBT_PCIe1 0x9A25
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device pci 07.1 on end # TBT_PCIe1 0x9A25
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device pci 07.2 off end # TBT_PCIe2 0x9A27
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device pci 07.2 on end # TBT_PCIe2 0x9A27
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device pci 07.3 off end # TBT_PCIe3 0x9A29
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device pci 07.3 on end # TBT_PCIe3 0x9A29
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device pci 08.0 off end # GNA 0x9A11
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device pci 08.0 off end # GNA 0x9A11
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device pci 09.0 off end # NPK 0x9A33
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device pci 09.0 off end # NPK 0x9A33
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device pci 0a.0 off end # Crash-log SRAM 0x9A0D
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device pci 0a.0 off end # Crash-log SRAM 0x9A0D
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device pci 0d.0 on end # USB xHCI 0x9A13
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device pci 0d.0 on end # USB xHCI 0x9A13
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device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
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device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
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device pci 0d.2 off end # TBT DMA0 0x9A1B
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device pci 0d.2 on end # TBT DMA0 0x9A1B
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device pci 0d.3 off end # TBT DMA1 0x9A1D
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device pci 0d.3 on end # TBT DMA1 0x9A1D
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device pci 0e.0 off end # VMD 0x9A0B
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device pci 0e.0 off end # VMD 0x9A0B
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# From PCH EDS(576591)
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# From PCH EDS(576591)
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@ -105,13 +105,14 @@ chip soc/intel/tigerlake
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[PchSerialIoIndexUART2] = PchSerialIoPci,
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[PchSerialIoIndexUART2] = PchSerialIoPci,
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}"
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}"
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# TCSS USB3
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register "TcssXhciEn" = "1"
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register "TcssAuxOri" = "0"
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# D3Hot and D3Cold for TCSS
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# D3Hot and D3Cold for TCSS
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register "TcssD3HotEnable" = "1"
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register "TcssD3HotEnable" = "1"
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register "TcssD3ColdEnable" = "1"
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register "TcssD3ColdEnable" = "1"
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# TCSS USB3
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register "TcssAuxOri" = "0"
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#HD Audio
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#HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaDspEnable" = "1"
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register "PchHdaAudioLinkHdaEnable" = "0"
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register "PchHdaAudioLinkHdaEnable" = "0"
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@ -149,17 +150,17 @@ chip soc/intel/tigerlake
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device pci 04.0 on end # DPTF 0x9A03
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device pci 04.0 on end # DPTF 0x9A03
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device pci 05.0 on end # IPU 0x9A19
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device pci 05.0 on end # IPU 0x9A19
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device pci 06.0 on end # PEG60 0x9A09
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device pci 06.0 on end # PEG60 0x9A09
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device pci 07.0 off end # TBT_PCIe0 0x9A23
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device pci 07.0 on end # TBT_PCIe0 0x9A23
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device pci 07.1 off end # TBT_PCIe1 0x9A25
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device pci 07.1 on end # TBT_PCIe1 0x9A25
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device pci 07.2 off end # TBT_PCIe2 0x9A27
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device pci 07.2 on end # TBT_PCIe2 0x9A27
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device pci 07.3 off end # TBT_PCIe3 0x9A29
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device pci 07.3 on end # TBT_PCIe3 0x9A29
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device pci 08.0 off end # GNA 0x9A11
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device pci 08.0 off end # GNA 0x9A11
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device pci 09.0 off end # NPK 0x9A33
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device pci 09.0 off end # NPK 0x9A33
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device pci 0a.0 off end # Crash-log SRAM 0x9A0D
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device pci 0a.0 off end # Crash-log SRAM 0x9A0D
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device pci 0d.0 on end # USB xHCI 0x9A13
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device pci 0d.0 on end # USB xHCI 0x9A13
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device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
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device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
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device pci 0d.2 off end # TBT DMA0 0x9A1B
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device pci 0d.2 on end # TBT DMA0 0x9A1B
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device pci 0d.3 off end # TBT DMA1 0x9A1D
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device pci 0d.3 on end # TBT DMA1 0x9A1D
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device pci 0e.0 off end # VMD 0x9A0B
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device pci 0e.0 off end # VMD 0x9A0B
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# From PCH EDS(576591)
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# From PCH EDS(576591)
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