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mb/google/brya/var/kinox: Reconfigure GPIO settings 

Configure GPIOs according to updated schematics.
- GPP_A21 from NC to TCP_DP1_CTRLCLK.
- GPP_A22 from NC to TCP_DP1_CTRLDATA.
- GPP_E22 from DDIA_DP_CTRLCLK to NC.
- GPP_E23 from DDIA_DP_CTRLDATA to NC.

BUG=b:214025396
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Dtrain Hsu 2022-03-11 13:45:18 +08:00 committed by Felix Held
parent 2b19d547c0
commit b24e45d215
1 changed files with 4 additions and 8 deletions
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12
src/mainboard/google/brya/variants/kinox/gpio.c
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@ -16,10 +16,10 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_A19, NONE), PAD_NC(GPP_A19, NONE),
/* A20 : DDSP_HPD2 ==> NC */ /* A20 : DDSP_HPD2 ==> NC */
PAD_NC(GPP_A20, NONE), PAD_NC(GPP_A20, NONE),
/* A21 : DDPC_CTRCLK ==> NC */ /* A21 : DDPC_CTRCLK ==> TCP_DP1_CTRLCLK */
PAD_NC(GPP_A21, NONE), PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
/* A22 : DDPC_CTRLDATA ==> NC */ /* A22 : DDPC_CTRLDATA ==> TCP_DP1_CTRLDATA */
PAD_NC(GPP_A22, NONE), PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
/* B2 : VRALERT# ==> TP153 */ /* B2 : VRALERT# ==> TP153 */
PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B2, NONE),
@ -56,10 +56,6 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E20, NONE), PAD_NC(GPP_E20, NONE),
/* E21 : DDP2_CTRLDATA ==> NC */ /* E21 : DDP2_CTRLDATA ==> NC */
PAD_NC(GPP_E21, NONE), PAD_NC(GPP_E21, NONE),
/* E22 : DDPA_CTRLCLK ==> DDIA_DP_CTRLCLK */
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
/* E23 : DDPA_CTRLDATA ==> DDIA_DP_CTRLDATA */
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
/* F11 : THC1_SPI2_CLK ==> NC */ /* F11 : THC1_SPI2_CLK ==> NC */
PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),