link: Support native raminit
Change-Id: I95173c06d334a340fa2157511a1d69f38877b264 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13665 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -16,10 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SERIRQ_CONTINUOUS_MODE
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select SERIRQ_CONTINUOUS_MODE
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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config USE_NATIVE_RAMINIT
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bool
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default n
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config CHROMEOS
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config CHROMEOS
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select CHROMEOS_VBNV_CMOS
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select CHROMEOS_VBNV_CMOS
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select LID_SWITCH
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select LID_SWITCH
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@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x00000200"
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register "gpu_cpu_backlight" = "0x00000200"
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register "gpu_pch_backlight" = "0x04000000"
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register "gpu_pch_backlight" = "0x04000000"
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register "max_mem_clock_mhz" = "666"
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device cpu_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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device lapic 0 on end
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@ -29,6 +29,7 @@
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#include <console/console.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include "ec/google/chromeec/ec.h"
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#include "ec/google/chromeec/ec.h"
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@ -115,10 +116,10 @@ void rcba_config(void)
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RCBA32(FD) = reg32;
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RCBA32(FD) = reg32;
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}
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}
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static void copy_spd(struct pei_data *peid)
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static uint8_t *locate_spd(void)
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{
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{
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const int gpio_vector[] = {41, 42, 43, 10, -1};
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const int gpio_vector[] = {41, 42, 43, 10, -1};
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char *spd_file;
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uint8_t *spd_file;
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size_t spd_file_len;
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size_t spd_file_len;
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int spd_index = get_gpios(gpio_vector);
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int spd_index = get_gpios(gpio_vector);
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@ -128,18 +129,15 @@ static void copy_spd(struct pei_data *peid)
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if (!spd_file)
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if (!spd_file)
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die("SPD data not found.");
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die("SPD data not found.");
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if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
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if (spd_file_len < ((spd_index + 1) * 256)) {
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printk(BIOS_ERR, "spd index override to 0 - old hardware?\n");
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printk(BIOS_ERR, "spd index override to 0 - old hardware?\n");
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spd_index = 0;
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spd_index = 0;
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}
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}
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if (spd_file_len < sizeof(peid->spd_data[0]))
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if (spd_file_len < 256)
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die("Missing SPD data.");
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die("Missing SPD data.");
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memcpy(peid->spd_data[0],
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return spd_file + spd_index * 256;
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spd_file +
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spd_index * sizeof(peid->spd_data[0]),
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sizeof(peid->spd_data[0]));
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}
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}
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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@ -190,7 +188,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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},
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},
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};
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};
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*pei_data = pei_data_template;
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*pei_data = pei_data_template;
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copy_spd(pei_data);
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memcpy(pei_data->spd_data[0], locate_spd(),
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sizeof(pei_data->spd_data[0]));
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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/* enabled power usb oc pin */
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{ 0, 0, -1 }, /* P0: Empty */
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{ 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
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{ 1, 0, 1 }, /* P2: Left USB 2 (OC1) */
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{ 1, 0, -1 }, /* P3: SDCARD (no OC) */
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{ 0, 0, -1 }, /* P4: Empty */
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{ 1, 0, -1 }, /* P5: WWAN (no OC) */
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{ 0, 0, -1 }, /* P6: Empty */
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{ 0, 0, -1 }, /* P7: Empty */
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{ 1, 0, -1 }, /* P8: Camera (no OC) */
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{ 1, 0, -1 }, /* P9: Bluetooth (no OC) */
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{ 0, 0, -1 }, /* P10: Empty */
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{ 0, 0, -1 }, /* P11: Empty */
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{ 0, 0, -1 }, /* P12: Empty */
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{ 0, 0, -1 }, /* P13: Empty */
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};
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void mainboard_get_spd(spd_raw_data *spd) {
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memcpy(&spd[0], locate_spd(), 128);
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}
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}
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void mainboard_early_init(int s3resume)
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void mainboard_early_init(int s3resume)
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