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ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case 

Currently the code in the if statement

    if (!byte)
    	do_smbus_write_byte(0xb20, 0x15, 0x3, byte);

only gets executed if `byte == 0x0`, that means only in the
default case where RAM voltage is 1.5 Volts. But the RAM voltage
should be changed when configured for the non-default case.

So negate the predicate to alter the RAM voltage for the
non-default cases.

To prevent the build error

    OBJCOPY    cbfs/fallback/coreboot_ram.elf
    coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main':
    /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1

add `southbridge/amd/agesa/hudson/smbus.c` providing the function
`do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can
actually be used after the needed header files are included in a
previous commit.

Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6
Reported-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3200
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
This commit is contained in:
Paul Menzel 2013-05-05 12:09:16 +02:00 committed by Martin Roth
parent 963bed546f
commit b2cddd4c12
2 changed files with 3 additions and 1 deletions
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3
src/mainboard/asus/f2a85-m/romstage.c
View File

@ -101,7 +101,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* set DDR3 voltage */ /* set DDR3 voltage */
byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
if (!byte) /* default is byte = 0x0, so no need to set it in this case */
if (byte)
do_smbus_write_byte(0xb20, 0x15, 0x3, byte); do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
} }

1
src/southbridge/amd/agesa/hudson/Makefile.inc
View File

@ -1,3 +1,4 @@
romstage-y += smbus.c
ramstage-y += hudson.c ramstage-y += hudson.c
ramstage-y += usb.c ramstage-y += usb.c
ramstage-y += lpc.c ramstage-y += lpc.c