arm64: split cpu.c
The cpu.c contains some helpful construts as well as ramstage devicetree handling. Split the 2 pieces so that cpu.c can be reused in secmon. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted. Change-Id: Iec0f8462411897a255f7aa289191ce6761e08bb0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4f30f1186950424b65df6858965a09ca51637e4f Original-Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218842 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9089 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin
Patrick Georgi
parent
4f89d97c06
commit
b30c9b1c9a
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@ -116,6 +116,7 @@ ramstage-y += c_entry.c
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ramstage-y += stages.c
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ramstage-y += div0.c
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ramstage-y += cpu.c
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ramstage-y += cpu_ramstage.c
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ramstage-y += eabi_compat.c
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ramstage-y += boot.c
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ramstage-y += tables.c
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@ -19,163 +19,19 @@
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#include <stdint.h>
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#include <stdlib.h>
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#include <arch/barrier.h>
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#include <arch/lib_helpers.h>
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#include <cpu/cpu.h>
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#include <console/console.h>
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#include <gic.h>
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#include "cpu-internal.h"
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static struct cpu_info cpu_infos[CONFIG_MAX_CPUS];
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struct cpu_info cpu_infos[CONFIG_MAX_CPUS];
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struct cpu_info *bsp_cpu_info;
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static inline struct cpu_info *cpu_info_for_cpu(unsigned int id)
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{
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return &cpu_infos[id];
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}
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struct cpu_info *cpu_info(void)
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{
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return cpu_info_for_cpu(smp_processor_id());
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}
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static int cpu_online(struct cpu_info *ci)
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{
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return load_acquire(&ci->online) != 0;
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}
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static void cpu_mark_online(struct cpu_info *ci)
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{
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store_release(&ci->online, 1);
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}
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static inline void cpu_disable_dev(device_t dev)
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{
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dev->enabled = 0;
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}
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static struct cpu_driver *locate_cpu_driver(uint32_t midr)
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{
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struct cpu_driver *cur;
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for (cur = cpu_drivers; cur != ecpu_drivers; cur++) {
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const struct cpu_device_id *id_table = cur->id_table;
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for (; id_table->midr != CPU_ID_END; id_table++) {
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if (id_table->midr == midr)
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return cur;
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}
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}
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return NULL;
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}
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static int cpu_set_device_operations(device_t dev)
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{
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uint32_t midr;
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struct cpu_driver *driver;
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midr = raw_read_midr_el1();
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driver = locate_cpu_driver(midr);
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if (driver == NULL) {
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printk(BIOS_WARNING, "No CPU driver for MIDR %08x\n", midr);
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return -1;
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}
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dev->ops = driver->ops;
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return 0;
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}
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/* Set up default SCR values. */
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static void el3_init(void)
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{
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uint32_t scr;
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if (get_current_el() != EL3)
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return;
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scr = raw_read_scr_el3();
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/* Default to non-secure EL1 and EL0. */
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scr &= ~(SCR_NS_MASK);
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scr |= SCR_NS_ENABLE;
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/* Disable IRQ, FIQ, and external abort interrupt routing. */
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scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK);
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scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE;
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/* Enable HVC */
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scr &= ~(SCR_HVC_MASK);
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scr |= SCR_HVC_ENABLE;
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/* Disable SMC */
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scr &= ~(SCR_SMC_MASK);
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scr |= SCR_SMC_DISABLE;
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/* Disable secure instruction fetches. */
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scr &= ~(SCR_SIF_MASK);
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scr |= SCR_SIF_DISABLE;
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/* All lower exception levels 64-bit by default. */
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scr &= ~(SCR_RW_MASK);
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scr |= SCR_LOWER_AARCH64;
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/* Disable secure EL1 access to secure timer. */
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scr &= ~(SCR_ST_MASK);
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scr |= SCR_ST_DISABLE;
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/* Don't trap on WFE or WFI instructions. */
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scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK);
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scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE;
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raw_write_scr_el3(scr);
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isb();
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}
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static void init_this_cpu(void *arg)
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{
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struct cpu_info *ci = arg;
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device_t dev = ci->cpu;
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cpu_set_device_operations(dev);
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el3_init();
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/* Initialize the GIC. */
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gic_init();
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if (dev->ops != NULL && dev->ops->init != NULL) {
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dev->initialized = 1;
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printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
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dev->ops->init(dev);
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}
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}
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/* Fill in cpu_info structures according to device tree. */
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static void init_cpu_info(struct bus *bus)
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{
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device_t cur;
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for (cur = bus->children; cur != NULL; cur = cur->sibling) {
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struct cpu_info *ci;
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unsigned int id = cur->path.cpu.id;
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if (cur->path.type != DEVICE_PATH_CPU)
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continue;
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/* IDs are currently mapped 1:1 with logical CPU numbers. */
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if (id >= CONFIG_MAX_CPUS) {
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printk(BIOS_WARNING,
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"CPU id %x too large. Disabling.\n", id);
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cpu_disable_dev(cur);
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continue;
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}
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ci = cpu_info_for_cpu(id);
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if (ci->cpu != NULL) {
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printk(BIOS_WARNING,
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"Duplicate ID %x in device tree.\n", id);
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cpu_disable_dev(cur);
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}
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ci->cpu = cur;
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ci->id = cur->path.cpu.id;
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}
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/* Mark current cpu online. */
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cpu_mark_online(cpu_info());
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}
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static inline int action_queue_empty(struct cpu_action_queue *q)
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{
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return load_acquire_exclusive(&q->todo) == NULL;
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@ -246,8 +102,8 @@ static void action_run_on_cpu(struct cpu_info *ci, struct cpu_action *action,
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{
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struct cpu_action_queue *q = &ci->action_queue;
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/* Don't run actions on non-online or enabled devices. */
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if (!cpu_online(ci) || ci->cpu == NULL || !ci->cpu->enabled)
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/* Don't run actions on non-online cpus. */
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if (!cpu_online(ci))
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return;
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if (ci->id == smp_processor_id()) {
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@ -333,14 +189,12 @@ int arch_run_on_all_cpus_but_self_async(struct cpu_action *action)
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return __arch_run_on_all_cpus_but_self(action, 0);
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}
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void arch_secondary_cpu_init(void)
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void arch_cpu_wait_for_action(void)
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{
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struct cpu_info *ci = cpu_info();
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struct cpu_action_queue *q = &ci->action_queue;
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/* Mark this CPU online. */
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cpu_mark_online(ci);
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while (1) {
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struct cpu_action *orig;
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struct cpu_action action;
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@ -351,72 +205,3 @@ void arch_secondary_cpu_init(void)
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action_queue_complete(q, orig);
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}
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}
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void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
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{
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size_t max_cpus;
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size_t i;
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struct cpu_info *ci;
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void (*entry)(void);
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struct bus *bus;
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if (cluster->path.type != DEVICE_PATH_CPU_CLUSTER) {
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printk(BIOS_ERR,
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"CPU init failed. Device is not a CPU_CLUSTER: %s\n",
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dev_path(cluster));
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return;
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}
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bus = cluster->link_list;
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/* Check if no children under this device. */
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if (bus == NULL)
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return;
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entry = prepare_secondary_cpu_startup();
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/* Initialize the cpu_info structures. */
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init_cpu_info(bus);
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max_cpus = cntrl_ops->total_cpus();
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if (max_cpus > CONFIG_MAX_CPUS) {
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printk(BIOS_WARNING,
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"max_cpus (%zu) exceeds CONFIG_MAX_CPUS (%zu).\n",
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max_cpus, (size_t)CONFIG_MAX_CPUS);
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max_cpus = CONFIG_MAX_CPUS;
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}
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for (i = 0; i < max_cpus; i++) {
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device_t dev;
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struct cpu_action action;
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ci = cpu_info_for_cpu(i);
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dev = ci->cpu;
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/* Disregard CPUs not in device tree. */
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if (dev == NULL)
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continue;
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/* Skip disabled CPUs. */
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if (!dev->enabled)
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continue;
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if (!cpu_online(ci)) {
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/* Start the CPU. */
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printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id);
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if (cntrl_ops->start_cpu(ci->id, entry)) {
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printk(BIOS_ERR,
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"Failed to start CPU%x\n", ci->id);
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continue;
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}
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/* Wait for CPU to come online. */
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while (!cpu_online(ci));
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printk(BIOS_DEBUG, "CPU%x online.\n", ci->id);
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}
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/* Send it the init action. */
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action.run = init_this_cpu;
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action.arg = ci;
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action_run_on_cpu(ci, &action, 1);
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}
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}
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@ -0,0 +1,230 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <arch/lib_helpers.h>
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#include <cpu/cpu.h>
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#include <console/console.h>
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#include <gic.h>
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#include "cpu-internal.h"
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static inline void cpu_disable_dev(device_t dev)
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{
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dev->enabled = 0;
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}
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static struct cpu_driver *locate_cpu_driver(uint32_t midr)
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{
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struct cpu_driver *cur;
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for (cur = cpu_drivers; cur != ecpu_drivers; cur++) {
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const struct cpu_device_id *id_table = cur->id_table;
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for (; id_table->midr != CPU_ID_END; id_table++) {
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if (id_table->midr == midr)
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return cur;
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}
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}
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return NULL;
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}
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static int cpu_set_device_operations(device_t dev)
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{
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uint32_t midr;
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struct cpu_driver *driver;
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midr = raw_read_midr_el1();
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driver = locate_cpu_driver(midr);
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if (driver == NULL) {
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printk(BIOS_WARNING, "No CPU driver for MIDR %08x\n", midr);
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return -1;
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}
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dev->ops = driver->ops;
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return 0;
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}
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/* Set up default SCR values. */
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static void el3_init(void)
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{
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uint32_t scr;
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if (get_current_el() != EL3)
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return;
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scr = raw_read_scr_el3();
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/* Default to non-secure EL1 and EL0. */
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scr &= ~(SCR_NS_MASK);
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scr |= SCR_NS_ENABLE;
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/* Disable IRQ, FIQ, and external abort interrupt routing. */
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scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK);
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scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE;
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/* Enable HVC */
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scr &= ~(SCR_HVC_MASK);
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scr |= SCR_HVC_ENABLE;
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/* Disable SMC */
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scr &= ~(SCR_SMC_MASK);
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scr |= SCR_SMC_DISABLE;
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/* Disable secure instruction fetches. */
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scr &= ~(SCR_SIF_MASK);
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scr |= SCR_SIF_DISABLE;
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/* All lower exception levels 64-bit by default. */
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scr &= ~(SCR_RW_MASK);
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scr |= SCR_LOWER_AARCH64;
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/* Disable secure EL1 access to secure timer. */
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scr &= ~(SCR_ST_MASK);
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scr |= SCR_ST_DISABLE;
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/* Don't trap on WFE or WFI instructions. */
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scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK);
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scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE;
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raw_write_scr_el3(scr);
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isb();
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}
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static void init_this_cpu(void *arg)
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{
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struct cpu_info *ci = arg;
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device_t dev = ci->cpu;
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cpu_set_device_operations(dev);
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el3_init();
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/* Initialize the GIC. */
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gic_init();
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if (dev->ops != NULL && dev->ops->init != NULL) {
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dev->initialized = 1;
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printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
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dev->ops->init(dev);
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}
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}
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/* Fill in cpu_info structures according to device tree. */
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static void init_cpu_info(struct bus *bus)
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{
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device_t cur;
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for (cur = bus->children; cur != NULL; cur = cur->sibling) {
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struct cpu_info *ci;
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unsigned int id = cur->path.cpu.id;
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if (cur->path.type != DEVICE_PATH_CPU)
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continue;
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/* IDs are currently mapped 1:1 with logical CPU numbers. */
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if (id >= CONFIG_MAX_CPUS) {
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printk(BIOS_WARNING,
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"CPU id %x too large. Disabling.\n", id);
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cpu_disable_dev(cur);
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continue;
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}
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ci = cpu_info_for_cpu(id);
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if (ci->cpu != NULL) {
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printk(BIOS_WARNING,
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"Duplicate ID %x in device tree.\n", id);
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cpu_disable_dev(cur);
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}
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ci->cpu = cur;
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ci->id = cur->path.cpu.id;
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}
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/* Mark current cpu online. */
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cpu_mark_online(cpu_info());
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}
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void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops)
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{
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size_t max_cpus;
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size_t i;
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struct cpu_info *ci;
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void (*entry)(void);
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struct bus *bus;
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if (cluster->path.type != DEVICE_PATH_CPU_CLUSTER) {
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printk(BIOS_ERR,
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"CPU init failed. Device is not a CPU_CLUSTER: %s\n",
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dev_path(cluster));
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return;
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}
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bus = cluster->link_list;
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/* Check if no children under this device. */
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if (bus == NULL)
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return;
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entry = prepare_secondary_cpu_startup();
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/* Initialize the cpu_info structures. */
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init_cpu_info(bus);
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max_cpus = cntrl_ops->total_cpus();
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if (max_cpus > CONFIG_MAX_CPUS) {
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printk(BIOS_WARNING,
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"max_cpus (%zu) exceeds CONFIG_MAX_CPUS (%zu).\n",
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max_cpus, (size_t)CONFIG_MAX_CPUS);
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max_cpus = CONFIG_MAX_CPUS;
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}
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for (i = 0; i < max_cpus; i++) {
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device_t dev;
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struct cpu_action action;
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ci = cpu_info_for_cpu(i);
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dev = ci->cpu;
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/* Disregard CPUs not in device tree. */
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if (dev == NULL)
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continue;
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/* Skip disabled CPUs. */
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if (!dev->enabled)
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continue;
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if (!cpu_online(ci)) {
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/* Start the CPU. */
|
||||
printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id);
|
||||
if (cntrl_ops->start_cpu(ci->id, entry)) {
|
||||
printk(BIOS_ERR,
|
||||
"Failed to start CPU%x\n", ci->id);
|
||||
continue;
|
||||
}
|
||||
/* Wait for CPU to come online. */
|
||||
while (!cpu_online(ci));
|
||||
printk(BIOS_DEBUG, "CPU%x online.\n", ci->id);
|
||||
}
|
||||
|
||||
/* Send it the init action. */
|
||||
action.run = init_this_cpu;
|
||||
action.arg = ci;
|
||||
arch_run_on_cpu(ci->id, &action);
|
||||
}
|
||||
}
|
||||
|
||||
void arch_secondary_cpu_init(void)
|
||||
{
|
||||
/* Mark this CPU online. */
|
||||
cpu_mark_online(cpu_info());
|
||||
|
||||
arch_cpu_wait_for_action();
|
||||
}
|
||||
|
|
@ -23,6 +23,7 @@
|
|||
#define asmlinkage
|
||||
|
||||
#if !defined(__PRE_RAM__)
|
||||
#include <arch/barrier.h>
|
||||
#include <device/device.h>
|
||||
|
||||
enum {
|
||||
|
|
@ -67,6 +68,12 @@ struct cpu_info {
|
|||
struct cpu_info *cpu_info(void);
|
||||
|
||||
extern struct cpu_info *bsp_cpu_info;
|
||||
extern struct cpu_info cpu_infos[CONFIG_MAX_CPUS];
|
||||
|
||||
static inline struct cpu_info *cpu_info_for_cpu(unsigned int id)
|
||||
{
|
||||
return &cpu_infos[id];
|
||||
}
|
||||
|
||||
/* Ran only by BSP at initial boot strapping. */
|
||||
static inline void cpu_set_bsp(void)
|
||||
|
|
@ -79,6 +86,16 @@ static inline int cpu_is_bsp(void)
|
|||
return cpu_info() == bsp_cpu_info;
|
||||
}
|
||||
|
||||
static inline int cpu_online(struct cpu_info *ci)
|
||||
{
|
||||
return load_acquire(&ci->online) != 0;
|
||||
}
|
||||
|
||||
static inline void cpu_mark_online(struct cpu_info *ci)
|
||||
{
|
||||
store_release(&ci->online, 1);
|
||||
}
|
||||
|
||||
/* Control routines for starting CPUs. */
|
||||
struct cpu_control_ops {
|
||||
/* Return the maximum number of CPUs supported. */
|
||||
|
|
@ -112,6 +129,9 @@ int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action);
|
|||
int arch_run_on_all_cpus_async(struct cpu_action *action);
|
||||
int arch_run_on_all_cpus_but_self_async(struct cpu_action *action);
|
||||
|
||||
/* Wait for actions to be perfomed. */
|
||||
void arch_cpu_wait_for_action(void);
|
||||
|
||||
#endif /* !__PRE_RAM__ */
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue