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soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register 

Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Elyes HAOUAS 2020-04-28 09:42:47 +02:00 committed by Patrick Georgi
parent a15eaec1e6
commit b30d054584
1 changed files with 4 additions and 3 deletions
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7
src/soc/amd/stoneyridge/psp.c
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@ -12,7 +12,8 @@
void soc_enable_psp_early(void)
{
u32 base, limit, cmd;
u32 base, limit;
u16 cmd;
/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
@ -25,9 +26,9 @@ void soc_enable_psp_early(void)
pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
/* Enable memory access and master */
cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND);
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd);
};
void *soc_get_mbox_address(void)