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mainboard/google/zoombini: Add SoC acpi files to dsdt.asl 

BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.

Change-Id: I417a1c606e4968120414af57aa3b17d5c3b3cad0
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Nick Vaccaro 2017-12-28 20:28:20 -08:00 committed by Martin Roth
parent 7f61fb99d5
commit b331923c69
1 changed files with 11 additions and 0 deletions
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11
src/mainboard/google/zoombini/dsdt.asl
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@ -24,14 +24,25 @@ DefinitionBlock(
0x20110725 // OEM revision 0x20110725 // OEM revision
) )
{ {
// Some generic macros
#include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables // global NVS and variables
#include <soc/intel/cannonlake/acpi/globalnvs.asl> #include <soc/intel/cannonlake/acpi/globalnvs.asl>
Scope (\_SB) { Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/cannonlake/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
} }
#if IS_ENABLED(CONFIG_CHROMEOS) #if IS_ENABLED(CONFIG_CHROMEOS)
// Chrome OS specific // Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif #endif
// Chipset specific sleep states
#include <soc/intel/cannonlake/acpi/sleepstates.asl>
} }