GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/x4x,sandybridge: Move INITRAM timestamps 

Let's not have CBMEM hooks in between the different
INITRAM timestamps.

Change-Id: I46db196bcdf60361429b8a81772fa66d252ef1a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-02-17 20:43:04 +02:00
parent 4ce0a07f06
commit b33c6fbfd5
4 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/northbridge/intel/sandybridge/raminit.c
View File

@ -298,6 +298,8 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
size_t mrc_size;
ramctr_timing *ctrl_cached = NULL;
timestamp_add_now(TS_BEFORE_INITRAM);
MCHBAR32(SAPMCTL) |= 1;
/* Wait for ME to be ready */
@ -458,6 +460,8 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
report_memory_config();
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_was_inited = !cbmem_recovery(s3resume);
if (!fast_boot)
save_timings(&ctrl);
@ -473,8 +477,5 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
void perform_raminit(int s3resume)
{
post_code(0x3a);
timestamp_add_now(TS_BEFORE_INITRAM);
init_dram_ddr3(s3resume, cpu_get_cpuid());
}

1
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@ -361,6 +361,7 @@ void perform_raminit(int s3resume)
pei_data.boot_mode = s3resume ? 2 : 0;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
/* Sanity check mrc_var location by verifying a known field */
mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE;

3
src/northbridge/intel/sandybridge/romstage.c
View File

@ -5,7 +5,6 @@
#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <romstage_handoff.h>
#include <timestamp.h>
#include "sandybridge.h"
#include <arch/romstage.h>
#include <device/pci_def.h>
@ -63,8 +62,6 @@ void mainboard_romstage_entry(void)
perform_raminit(s3resume);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3b);
/* Perform some initialization that must run before stage2 */
early_pch_reset_pmcon();

3
src/northbridge/intel/x4x/raminit.c
View File

@ -684,6 +684,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
pci_or_config8(HOST_BRIDGE, 0xf4, 1);
timestamp_add_now(TS_AFTER_INITRAM);
printk(BIOS_DEBUG, "RAM initialization finished.\n");
cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME);
@ -695,6 +697,5 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
system_reset();
}
timestamp_add_now(TS_AFTER_INITRAM);
printk(BIOS_DEBUG, "Memory initialized\n");
}