soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T
The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size. FSP-M seems to have a very large stack usage so it would overflow other car symbols located below the coreboot stack such as timestamps and the pre-ram console, which are now fixed. TEST: boot with ocp/deltalake. Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -27,22 +27,25 @@ config PCR_BASE_ADDRESS
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config DCACHE_RAM_BASE
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hex
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default 0xfe8b0000
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default 0xfe800000
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config DCACHE_RAM_SIZE
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hex
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default 0x170000
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default 0x1fff00
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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and/or romstage. FSP-T reserves the upper 0x100 for
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FspReservedBuffer.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0xA0000
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default 0x140000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages. It needs to include FSP-M stack requirement and
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CB romstage stack requirement.
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CB romstage stack requirement. The integration documentation
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says this needs to be 256KiB, but practice show this needs to
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be a lot more.
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config CPU_MICROCODE_CBFS_LOC
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hex
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@ -67,11 +70,13 @@ config STACK_SIZE
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config FSP_TEMP_RAM_SIZE
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hex
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depends on FSP_USES_CB_STACK
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default 0xA0000
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default 0x40000
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help
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The amount of anticipated heap usage in CAR by FSP.
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Refer to Platform FSP integration guide document to know
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the exact FSP requirement for Heap setup.
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the exact FSP requirement for Heap setup. The FSP integration
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documentation says this needs to be at least 128KiB, but practice
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show this needs to be 256KiB or more.
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config SOC_INTEL_COMMON_BLOCK_P2SB
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def_bool y
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