soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -8,6 +8,7 @@ romstage-y += port_descriptors.c
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ramstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += port_descriptors.c
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ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin),)
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ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin),)
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APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin
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APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin
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@ -6,6 +6,7 @@ romstage-y += port_descriptors.c
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ramstage-y += mainboard.c
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ramstage-y += mainboard.c
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ramstage-y += ec.c
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ramstage-y += ec.c
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ramstage-y += port_descriptors.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c
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verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c
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@ -75,6 +75,7 @@ config SOC_SPECIFIC_OPTIONS
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select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
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select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct
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@ -7,6 +7,7 @@
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#include <amdblocks/chip.h>
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#include <amdblocks/chip.h>
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#include <amdblocks/i2c.h>
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#include <amdblocks/i2c.h>
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#include <amdblocks/pci_clk_req.h>
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#include <gpio.h>
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#include <gpio.h>
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#include <soc/i2c.h>
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#include <soc/i2c.h>
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#include <soc/southbridge.h>
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#include <soc/southbridge.h>
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@ -92,11 +93,7 @@ struct soc_amd_mendocino_config {
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/* The array index is the general purpose PCIe clock output number. Values in here
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/* The array index is the general purpose PCIe clock output number. Values in here
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aren't the values written to the register to have the default to be always on. */
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aren't the values written to the register to have the default to be always on. */
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enum {
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enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
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GPP_CLK_ON, /* GPP clock always on; default */
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GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
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GPP_CLK_OFF, /* GPP clk off */
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} gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
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/* performance policy for the PCIe links: power consumption vs. link speed */
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/* performance policy for the PCIe links: power consumption vs. link speed */
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enum {
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enum {
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@ -6,6 +6,7 @@
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/amd_pci_util.h>
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#include <amdblocks/amd_pci_util.h>
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#include <amdblocks/gpio.h>
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#include <amdblocks/gpio.h>
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#include <amdblocks/pci_clk_req.h>
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#include <amdblocks/smi.h>
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#include <amdblocks/smi.h>
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#include <assert.h>
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#include <assert.h>
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#include <bootstate.h>
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#include <bootstate.h>
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@ -130,7 +131,7 @@ static void fch_init_acpi_ports(void)
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/* configure the general purpose PCIe clock outputs according to the devicetree settings */
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/* configure the general purpose PCIe clock outputs according to the devicetree settings */
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static void gpp_clk_setup(void)
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static void gpp_clk_setup(void)
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{
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{
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const struct soc_amd_mendocino_config *cfg = config_of_soc();
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struct soc_amd_mendocino_config *cfg = config_of_soc();
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/* look-up table to be able to iterate over the PCIe clock output settings */
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/* look-up table to be able to iterate over the PCIe clock output settings */
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const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
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const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
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@ -145,6 +146,8 @@ static void gpp_clk_setup(void)
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uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
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uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
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pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
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ARRAY_SIZE(cfg->gpp_clk_config));
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for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
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for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
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gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
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gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
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/*
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/*
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