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link/graphics: Add support for EDID 

This code is taken from an EDID reader written at Red Hat.

The key function is
int decode_edid(unsigned char *edid, int size, struct edid *out)

Which takes a pointer to an EDID blob, and a size, and decodes it into
a machine-independent format in out, which may be used for driving
chipsets. The EDID blob might come for IO, or a compiled-in EDID
BLOB, or CBFS.

Also included are the changes needed to use the EDID code on Link.

Change-Id: I66b275b8ed28fd77cfa5978bdec1eeef9e9425f1
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ronald G. Minnich 2013-03-13 14:35:01 -07:00 committed by Stefan Reinauer
parent a95a13bd47
commit b3b72f350e
5 changed files with 1857 additions and 362 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
src/include/edid.h Normal file
View File

@ -0,0 +1,66 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef EDID_H
#define EDID_H
/* structure for communicating EDID information from a raw EDID block to
* higher level functions.
* The size of the data types is not critical, so we leave them as
* unsigned int. We can move more into into this struct as needed.
*/
struct edid {
char manuf_name[4];
unsigned int model;
unsigned int serial;
unsigned int year;
unsigned int week;
unsigned int version[2];
unsigned int nonconformant;
unsigned int type;
unsigned int bpp;
unsigned int voltage;
unsigned int sync;
unsigned int xsize_cm;
unsigned int ysize_cm;
/* used to compute timing for graphics chips. */
unsigned char phsync;
unsigned char pvsync;
unsigned int ha;
unsigned int hbl;
unsigned int hso;
unsigned int hspw;
unsigned int hborder;
unsigned int va;
unsigned int vbl;
unsigned int vso;
unsigned int vspw;
unsigned int vborder;
/* it is unlikely we need these things. */
/* if one of these is non-zero, use that one. */
unsigned int aspect_landscape;
unsigned int aspect_portrait;
const char *range_class;
const char *syncmethod;
const char *stereo;
};
int decode_edid(unsigned char *edid, int size, struct edid *out);
#endif /* EDID_H */

1
src/lib/Makefile.inc
View File

@ -82,6 +82,7 @@ ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
ramstage-$(CONFIG_TRACE) += trace.c
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ramstage-$(CONFIG_COVERAGE) += libgcov.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c
ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c

1388
src/lib/edid.c Normal file
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File diff suppressed because it is too large Load Diff

99
src/mainboard/google/link/i915.c
View File

@ -45,6 +45,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/msr.h>
#include <edid.h>
#include "i915io.h"
enum {
@ -59,6 +60,18 @@ static unsigned short addrport;
static unsigned short dataport;
static unsigned int physbase;
extern int oprom_is_loaded;
static u32 htotal, hblank, hsync, vtotal, vblank, vsync;
const u32 link_edid_data[] = {
0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000,
0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259,
0x00545017, 0x01010000, 0x01010101, 0x01010101,
0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031,
0xb510003a, 0x19000010, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x4c00fe00,
0x69442047, 0x616c7073, 0x20200a79, 0xfe000000,
0x31504c00, 0x45513932, 0x50532d31, 0x24003141,
};
#define READ32(addr) io_i915_READ32(addr)
#define WRITE32(val, addr) io_i915_WRITE32(val, addr)
@ -90,27 +103,27 @@ void io_i915_WRITE32(unsigned long val, unsigned long addr)
/*
2560
4 words per
4 *p
10240
4k bytes per page
4096/p
2.50
1700 lines
1700 * p
4250.00
PTEs
2560
4 words per
4 *p
10240
4k bytes per page
4096/p
2.50
1700 lines
1700 * p
4250.00
PTEs
*/
static void
setgtt(int start, int end, unsigned long base, int inc)
{
int i;
int i;
for (i = start; i < end; i++){
u32 word = base + i*inc;
WRITE32(word|1,(i*4)|1);
}
for(i = start; i < end; i++){
u32 word = base + i*inc;
WRITE32(word|1,(i*4)|1);
}
}
static unsigned long tickspermicrosecond = 1795;
@ -178,12 +191,14 @@ static int run(int index)
int i, prev = 0;
struct iodef *id, *lastidread = 0;
unsigned long u, t;
if (index >= niodefs)
return index;
/* state machine! */
for(i = index, id = &iodefs[i]; id->op; i++, id++){
switch(id->op){
case M:
if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n",
globalmicroseconds(), id->msg);
globalmicroseconds(), id->msg);
break;
case P:
palette();
@ -213,11 +228,11 @@ static int run(int index)
if (verbose & vio)
printk(BIOS_SPEW, "PCH_PP_CONTROL\n");
switch(id->data & 0xf){
case 8: break;
case 7: break;
default: udelay(100000);
if (verbose & vio)
printk(BIOS_SPEW, "U %d\n", 100000);
case 8: break;
case 7: break;
default: udelay(100000);
if (verbose & vio)
printk(BIOS_SPEW, "U %d\n", 100000);
}
}
break;
@ -248,11 +263,13 @@ static int run(int index)
}
int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
unsigned int gfx);
unsigned int gfx);
int i915lightup(unsigned int pphysbase, unsigned int piobase,
unsigned int pmmio, unsigned int pgfx)
unsigned int pmmio, unsigned int pgfx)
{
static struct edid edid;
int index;
u32 auxin[16], auxout[16];
mmio = (void *)pmmio;
@ -260,13 +277,35 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
dataport = addrport + 4;
physbase = pphysbase;
graphics = pgfx;
printk(BIOS_SPEW,
"i915lightup: graphics %p mmio %p"
printk(BIOS_SPEW, "i915lightup: graphics %p mmio %p"
"addrport %04x physbase %08x\n",
(void *)graphics, mmio, addrport, physbase);
(void *)graphics, mmio, addrport, physbase);
globalstart = rdtscll();
decode_edid((unsigned char *)&link_edid_data, sizeof(link_edid_data), &edid);
htotal = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
hblank = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank);
hsync = (edid.ha + edid.hso - 1) |
((edid.ha + edid.hso + edid.hspw- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync);
vtotal = (edid.va - 1) | ((edid.va + edid.vbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal);
vblank = (edid.va - 1) | ((edid.va + edid.vbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank);
vsync = (edid.va + edid.vso - 1) |((edid.va + edid.vso + edid.vspw- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync);
printk(BIOS_SPEW, "Table has %d elements\n", niodefs);
index = run(0);
printk(BIOS_SPEW, "Run returns %d\n", index);
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_DPCD_REV<<8|0xe;
@ -328,8 +367,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
if (index != niodefs)
printk(BIOS_ERR, "Left over IO work in i915_lightup"
" -- this is likely a table error. "
"Only %d of %d were done.\n", index, niodefs);
" -- this is likely a table error. "
"Only %d of %d were done.\n", index, niodefs);
printk(BIOS_SPEW, "DONE startup\n");
verbose = 0;
/* GTT is the Global Translation Table for the graphics pipeline.
@ -357,7 +396,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
*/
setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n",
(void *)graphics, FRAME_BUFFER_BYTES);
(void *)graphics, FRAME_BUFFER_BYTES);
memset((void *)graphics, 0, FRAME_BUFFER_BYTES);
printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
i915_init_done = 1;

665
src/mainboard/google/link/i915io.c
View File

@ -21,337 +21,338 @@
#include "i915io.h"
struct iodef iodefs[] = {
{V, 0},
{W, 1, "", PCH_GMBUS0, 0x00000000, 0},
{R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0},
{R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0},
{W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0},
{M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0},
{R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10},
{W, 1, "", FORCEWAKE_MT, 0x00010001, 0},
{R, 1, "", FORCEWAKE_MT, 0x00010001, 0},
{R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0},
{R, 1, "", 0x13805c, 0x40000000, 0},
{R, 1, "", 0xa180, 0x84100020, 0},
{W, 1, "", FORCEWAKE_MT, 0x00010000, 0},
{R, 1, "", 0x120000, 0x00000000, 0},
{M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
{R, 1, "", 0x72008, 0x00000000, 0},
{W, 1, "", 0x72008, 0x00000000, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
{R, 1, "", 0x72008, 0x00000000, 0},
{W, 1, "", 0x72008, 0x00000000, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
{R, 1, "", 0x72008, 0x00000000, 0},
{W, 1, "", 0x72008, 0x00000000, 300},
{W, 1, "", CPU_VGACNTRL, 0x80000000, 0},
{R, 1, "", CPU_VGACNTRL, 0x80000000, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0},
{R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0},
{R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0},
{M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{I,},
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0},
{R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0},
{M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0},
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0},
{W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0},
{R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200},
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0},
{W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0},
{R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200},
{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", 0x9404, 0x00002000, 0},
{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
{W, 1, "", IVB_CHICKEN3, 0x00000024, 0},
{W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0},
{W, 1, "", 0xb01c, 0x3c4fff8c, 0},
{W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0},
{R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0},
{W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0},
{R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0},
{W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0},
{R, 1, "", _DSPAADDR, 0x00000000, 0},
{W, 1, "", _DSPAADDR, 0x00000000, 0},
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{R, 1, "", _DSPBCNTR, 0x00000000, 0},
{W, 1, "", _DSPBCNTR, 0x00004000, 0},
{R, 1, "", _DSPBADDR, 0x00000000, 0},
{W, 1, "", _DSPBADDR, 0x00000000, 0},
{R, 1, "", _DSPBSURF, 0x00000000, 0},
{W, 1, "", _DSPBSURF, 0x00000000, 0},
{R, 1, "", _DVSACNTR, 0x00000000, 0},
{W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0},
{R, 1, "", _DVSALINOFF, 0x00000000, 0},
{W, 1, "", _DVSALINOFF, 0x00000000, 0},
{R, 1, "", _DVSASURF, 0x00000000, 0},
{W, 1, "", _DVSASURF, 0x00000000, 0},
{W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0},
{R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0},
{W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0},
{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0},
{W, 1, "", _TRANSB_CHICKEN2, TRANS_AUTOTRAIN_GEN_STALL_DIS | 0x80000000, 0},
{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{I,},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_DP_D, 0x00000004, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
{M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0},
{W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0},
{W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0},
{W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0},
{W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0},
{W, 1, "", _PCH_FPA1, 0x00020e08, 0},
{W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0},
{W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0},
{W, 1, "", _HBLANK_A, 0x0a9f09ff, 0},
{W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0},
{W, 1, "", _VTOTAL_A, 0x06d406a3, 0},
{W, 1, "", _VBLANK_A, 0x06d406a3, 0},
{W, 1, "", _VSYNC_A, 0x06b006a6, 0},
{W, 1, "", _PIPEASRC, 0x09ff06a3, 0},
{W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0},
{W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0},
{W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0},
{W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0},
{M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
{R, 4562, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
{R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0},
{W, 1, "", _DSPASTRIDE, 0x00002800, 0},
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0},
{W, 1, "", _DSPAADDR, 0x00000000, 0},
{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0},
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
{M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{R, 1, "", _FDI_RXA_CTL, 0x00000040, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
{W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0},
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
{P, 1, "Set Palette"},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0},
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
{R, 4533, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0},
{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
{W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0},
{R, 1, "", _DSPAADDR, 0x00000000, 0},
{W, 1, "", _DSPAADDR, 0x00000000, 0},
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
{R, 4392, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
{M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0},
{R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0},
{R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0},
{R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0},
{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
{M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0},
{M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
{R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{I,},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{I,},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{I,},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{I,},
{M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
{I,},
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
{I,},
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
{I,},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
{I,},
{M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
{R, 1, "", _PIPEADSL, 0x00000633, 500},
{R, 1, "", _PIPEADSL, 0x00000652, 0},
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
{R, 5085, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
{I, 0, "(null)", 0x0, 0xcf8e64, 0}, };
{V, 0},
{W, 1, "", PCH_GMBUS0, 0x00000000, 0},
{R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0},
{R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0},
{W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0},
{M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0},
{R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10},
{W, 1, "", FORCEWAKE_MT, 0x00010001, 0},
{R, 1, "", FORCEWAKE_MT, 0x00010001, 0},
{R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0},
{R, 1, "", 0x13805c, 0x40000000, 0},
{R, 1, "", 0xa180, 0x84100020, 0},
{W, 1, "", FORCEWAKE_MT, 0x00010000, 0},
{R, 1, "", 0x120000, 0x00000000, 0},
{M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
{R, 1, "", 0x72008, 0x00000000, 0},
{W, 1, "", 0x72008, 0x00000000, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
{R, 1, "", 0x72008, 0x00000000, 0},
{W, 1, "", 0x72008, 0x00000000, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
{R, 1, "", 0x72008, 0x00000000, 0},
{W, 1, "", 0x72008, 0x00000000, 300},
{W, 1, "", CPU_VGACNTRL, 0x80000000, 0},
{R, 1, "", CPU_VGACNTRL, 0x80000000, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0},
{R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0},
{R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0},
{M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{I,},
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0},
{R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0},
{M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0},
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0},
{W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0},
{R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200},
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0},
{W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0},
{R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200},
{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", 0x9404, 0x00002000, 0},
{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
{W, 1, "", IVB_CHICKEN3, 0x00000024, 0},
{W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0},
{W, 1, "", 0xb01c, 0x3c4fff8c, 0},
{W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0},
{R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0},
{W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0},
{R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0},
{W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0},
{R, 1, "", _DSPAADDR, 0x00000000, 0},
{W, 1, "", _DSPAADDR, 0x00000000, 0},
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{R, 1, "", _DSPBCNTR, 0x00000000, 0},
{W, 1, "", _DSPBCNTR, 0x00004000, 0},
{R, 1, "", _DSPBADDR, 0x00000000, 0},
{W, 1, "", _DSPBADDR, 0x00000000, 0},
{R, 1, "", _DSPBSURF, 0x00000000, 0},
{W, 1, "", _DSPBSURF, 0x00000000, 0},
{R, 1, "", _DVSACNTR, 0x00000000, 0},
{W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0},
{R, 1, "", _DVSALINOFF, 0x00000000, 0},
{W, 1, "", _DVSALINOFF, 0x00000000, 0},
{R, 1, "", _DVSASURF, 0x00000000, 0},
{W, 1, "", _DVSASURF, 0x00000000, 0},
{W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0},
{R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0},
{W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0},
{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0},
{W, 1, "", _TRANSB_CHICKEN2, TRANS_AUTOTRAIN_GEN_STALL_DIS | 0x80000000, 0},
{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{I,},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_DP_D, 0x00000004, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
{M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0},
{W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0},
{W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0},
{W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0},
{W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0},
{W, 1, "", _PCH_FPA1, 0x00020e08, 0},
{W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0},
{W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0},
{W, 1, "", _HBLANK_A, 0x0a9f09ff, 0},
{W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0},
{W, 1, "", _VTOTAL_A, 0x06d406a3, 0},
{W, 1, "", _VBLANK_A, 0x06d406a3, 0},
{W, 1, "", _VSYNC_A, 0x06b006a6, 0},
{W, 1, "", _PIPEASRC, 0x09ff06a3, 0},
{W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0},
{W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0},
{W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0},
{W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0},
{M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500},
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
{R, 4562, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
{R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0},
{W, 1, "", _DSPASTRIDE, 0x00002800, 0},
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0},
{W, 1, "", _DSPAADDR, 0x00000000, 0},
{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0},
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
{M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200},
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{R, 1, "", _FDI_RXA_CTL, 0x00000040, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
{W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0},
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
{P, 1, "Set Palette"},
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0},
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
{R, 4533, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0},
{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
{W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0},
{R, 1, "", _DSPAADDR, 0x00000000, 0},
{W, 1, "", _DSPAADDR, 0x00000000, 0},
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
{R, 4392, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
{M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0},
{R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0},
{R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0},
{R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0},
{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
{R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
{M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0},
{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0},
{M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
{R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{I,},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{I,},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{I,},
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
{I,},
{M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
{I,},
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
{I,},
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
{I,},
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
{I,},
{M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
{R, 1, "", _PIPEADSL, 0x00000633, 500},
{R, 1, "", _PIPEADSL, 0x00000652, 0},
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
{R, 5085, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
{I,},
};
int niodefs = sizeof (iodefs) / sizeof (iodefs[0]);