GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Rewrite i82801er_enable to do nothing if device does not have an enable/disable bit. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Steven J. Magnani 2005-09-21 13:50:38 +00:00
parent 7557331605
commit b3d2d4d441
1 changed files with 48 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

78
src/southbridge/intel/i82801er/i82801er.c
View File

@ -6,48 +6,58 @@
void i82801er_enable(device_t dev) void i82801er_enable(device_t dev)
{ {
device_t lpc_dev; unsigned int index = 0;
unsigned int index; uint8_t bHasDisableBit = 0;
uint16_t reg_old, reg; uint16_t cur_disable_mask, new_disable_mask;
// all 82801er device ares in bus 0 // all 82801er devices are in bus 0
unsigned int devfn; unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
devfn = PCI_DEVFN(0x1f, 0); // lpc device_t lpc_dev = dev_find_slot(0, devfn); // 0
lpc_dev = dev_find_slot(0, devfn); // 0 if (!lpc_dev)
if (!lpc_dev ) {
return; return;
}
#if 0
if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
(lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_1F0)) {
uint32_t id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_1F0 << 16))) {
return;
}
}
#endif
index = (dev->path.u.pci.devfn & 7); // Calculate disable bit position for specified device:function
if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f // NOTE: For ICH-5, only the following devices can be disabled:
if(index==0){ //1f0 // D31: F0, F1, F2, F3, F5, F6,
index = 14; // D29: F0, F1, F2, F3, F7
}
} else { // D=0x1d if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
index += 8; index = PCI_FUNC(dev->path.u.pci.devfn);
switch (index) {
case 0:
case 1:
case 2:
case 3:
case 5:
case 6:
bHasDisableBit = 1;
break;
default:
break;
};
if (index == 0)
index = 14; // D31:F0 bit is an exception
} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
if ((PCI_FUNC(dev->path.u.pci.devfn) < 4) || (PCI_FUNC(dev->path.u.pci.devfn) == 7))
bHasDisableBit = 1;
} }
reg_old = pci_read_config16(lpc_dev, FUNC_DIS); if (bHasDisableBit) {
reg = reg_old; cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
reg &= ~(1<<index); // enable it new_disable_mask = cur_disable_mask & ~(1<<index); // enable it
if (!dev->enabled) { if (!dev->enabled) {
reg |= (1<<index); // disable it new_disable_mask |= (1<<index); // disable it
}
if (new_disable_mask != cur_disable_mask) {
pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
} }
if (reg != reg_old) {
pci_write_config16(lpc_dev, FUNC_DIS, reg);
} }
reg = pci_read_config16(lpc_dev, FUNC_DIS);
} }
struct chip_operations southbridge_intel_i82801er_ops = { struct chip_operations southbridge_intel_i82801er_ops = {