urara: Configure clocks and MFIOs
Set elements: - UART1 clock dividers and MFIOs - SPIM1 clock dividers and MFIOs - USB clock dividers - System clock divider - System PLL - MIPS CPU PLL BUG=chrome-os-partner:31438 TEST=tested on Pisachio bring up board; UART, SPI NOR, SPI NAND, and USB have proper functionality. BRANCH=none Change-Id: Ib01186a652fd59295a4cafc3ca99b94aa9564f74 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 65e68d82f34bb40ef3cfb397ecf5df0c83201151 Original-Change-Id: Ia2c31bbbfc020dc4fd71c72b877414adfdfc42a8 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241423 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Ionela Voinescu
Patrick Georgi
parent
95c902261f
commit
b3f666b252
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@ -40,6 +40,10 @@ config MAINBOARD_PART_NUMBER
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string
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default "ImgTec Pistachio Virtual Platform"
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config BOOTBLOCK_MAINBOARD_INIT
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string
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default "mainboard/google/urara/bootblock.c"
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config DRAM_SIZE_MB
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int
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default 256
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@ -0,0 +1,142 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <stdint.h>
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#include <soc/clocks.h>
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#include <console/console.h>
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#define GPIO_BIT_EN_ADDR(bank) (0xB8101C00 + 0x200 + (0x24 * (bank)))
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/* MFIO definitions for UART0/1 */
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#define UART1_RXD_MFIO 59
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#define UART1_TXD_MFIO 60
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#define UART0_RXD_MFIO 55
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#define UART0_TXD_MFIO 56
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#define UART0_RTS_MFIO 57
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#define UART0_CTS_MFIO 58
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/* MFIO definitions for SPIM */
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#define SPIM1_D0_TXD_MFIO 5
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#define SPIM1_D1_RXD_MFIO 4
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#define SPIM1_MCLK_MFIO 3
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#define SPIM1_D2_MFIO 6
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#define SPIM1_D3_MFIO 7
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#define SPIM1_CS0_MFIO 0
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static void uart1_mfio_setup(void)
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{
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u32 reg, mfio_mask;
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/*
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* Disable GPIO for UART1 MFIOs
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* All UART MFIOs have MFIO/16 = 3, therefore we use GPIO pad 3
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* This is the primary function (0) of these MFIOs and therfore there
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* is no need to set up a function number in the corresponding
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* function select register.
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*/
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reg = read32(GPIO_BIT_EN_ADDR(3));
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mfio_mask = 1 << (UART1_RXD_MFIO % 16);
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mfio_mask |= 1 << (UART1_TXD_MFIO % 16);
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/* Clear relevant bits */
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reg &= ~mfio_mask;
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/*
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* Set corresponding bits in the upper half word
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* in order to be able to modify the chosen pins
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*/
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reg |= mfio_mask << 16;
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write32(GPIO_BIT_EN_ADDR(3), reg);
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}
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static void spim1_mfio_setup(void)
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{
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u32 reg, mfio_mask;
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/*
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* Disable GPIO for SPIM1 MFIOs
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* All SPFI1 MFIOs have MFIO/16 = 0, therefore we use GPIO pad 0
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* This is the primary function (0) of these MFIOs and therfore there
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* is no need to set up a function number in the corresponding
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* function select register.
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*/
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reg = read32(GPIO_BIT_EN_ADDR(0));
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/* Disable GPIO for UART0 MFIOs */
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mfio_mask = 1 << (SPIM1_D0_TXD_MFIO % 16);
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mfio_mask |= 1 << (SPIM1_D1_RXD_MFIO % 16);
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mfio_mask |= 1 << (SPIM1_MCLK_MFIO % 16);
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mfio_mask |= 1 << (SPIM1_D2_MFIO % 16);
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mfio_mask |= 1 << (SPIM1_D3_MFIO % 16);
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/* TODO: for the moment it only sets up CS0 (NOR) */
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/* There is no need for other CS lines in Coreboot */
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mfio_mask |= 1 << (SPIM1_CS0_MFIO % 16);
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/* Clear relevant bits */
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reg &= ~mfio_mask;
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/*
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* Set corresponding bits in the upper half word
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* in order to be able to modify the chosen pins
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*/
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reg |= mfio_mask << 16;
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write32(GPIO_BIT_EN_ADDR(0), reg);
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}
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static int init_clocks(void)
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{
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int ret;
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/*
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* Set up dividers for peripherals before setting up PLLs
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* in order to not over-clock them when enabling PLLs
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*/
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/* System PLL divided by 2 -> 400 MHz */
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/* The same frequency will be the input frequency for the SPFI block */
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system_clk_setup(1);
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/* System clock divided by 8 -> 50 MHz */
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ret = usb_clk_setup(7, 2, 7);
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if (ret != CLOCKS_OK)
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return ret;
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/* System PLL divided by 7 divided by 62 -> 1.8433 Mhz */
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uart1_clk_setup(6, 61);
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/* Setup system PLL at 800 MHz */
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ret = sys_pll_setup(2, 1);
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if (ret != CLOCKS_OK)
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return ret;
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/* Setup MIPS PLL at 550 MHz */
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ret = mips_pll_setup(2, 1, 13, 275);
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if (ret != CLOCKS_OK)
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return ret;
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return CLOCKS_OK;
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}
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static void bootblock_mainboard_init(void)
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{
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if (!init_clocks()) {
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/* Disable GPIO on the peripheral lines */
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uart1_mfio_setup();
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printk(BIOS_INFO, "Urara board: UART initialized!\n");
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spim1_mfio_setup();
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}
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}
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@ -20,6 +20,7 @@
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#
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# We enable CBFS_SPI_WRAPPER for Pistachio targets.
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bootblock-y += clocks.c
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bootblock-y += spi.c
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romstage-y += spi.c
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ramstage-y += spi.c
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@ -0,0 +1,344 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <soc/clocks.h>
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#include <timer.h>
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#include <delay.h>
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#include <assert.h>
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/* Definitions for PLL enable */
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#define PISTACHIO_CLOCK_SWITCH 0xB8144200
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#define SYS_EXTERN_PLL_BYPASS_MASK 0x00002000
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#define SYS_PLL_CTRL4_ADDR 0xB8144048
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#define SYS_INTERNAL_PLL_BYPASS_MASK 0x10000000
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#define SYS_PLL_PD_CTRL_ADDR 0xB8144044
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#define SYS_PLL_PD_CTRL_PD_MASK 0x0000003F
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#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
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#define MIPS_PLL_CTRL2_ADDR 0xB8144008
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#define MIPS_INTERNAL_PLL_BYPASS_MASK 0x10000000
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#define MIPS_PLL_PD_CTRL_ADDR 0xB8144004
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#define MIPS_PLL_PD_CTRL_PD_MASK 0x0F000000
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/* Definitions for PLL dividers */
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#define SYS_PLL_POSTDIV_ADDR 0xB8144040
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#define SYS_PLL_POSTDIV1_MASK 0x07000000
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#define SYS_PLL_POSTDIV1_SHIFT 24
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#define SYS_PLL_POSTDIV2_MASK 0x38000000
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#define SYS_PLL_POSTDIV2_SHIFT 27
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#define SYS_PLL_STATUS_ADDR 0xB8144038
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#define SYS_PLL_STATUS_LOCK_MASK 0x00000001
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#define MIPS_PLL_POSTDIV_ADDR 0xB8144004
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#define MIPS_PLL_POSTDIV1_MASK 0x001C0000
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#define MIPS_PLL_POSTDIV1_SHIFT 18
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#define MIPS_PLL_POSTDIV2_MASK 0x00E00000
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#define MIPS_PLL_POSTDIV2_SHIFT 21
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#define MIPS_PLL_STATUS_ADDR 0xB8144000
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#define MIPS_PLL_STATUS_LOCK_MASK 0x00000001
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#define MIPS_REFDIV_ADDR 0xB8144004
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#define MIPS_REFDIV_MASK 0x0000003F
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#define MIPS_REFDIV_SHIFT 0
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#define MIPS_FEEDBACK_ADDR 0xB8144004
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#define MIPS_FEEDBACK_MASK 0x0003FFC0
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#define MIPS_FEEDBACK_SHIFT 6
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/* Definitions for system clock setup */
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#define SYSCLKINTERNAL_CTRL_ADDR 0xB8144244
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#define SYSCLKINTERNAL_MASK 0X00000007
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/* Definitions for USB clock setup */
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#define USBPHYCLKOUT_CTRL_ADDR 0xB814422C
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#define USBPHYCLKOUT_MASK 0X0000003F
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#define USBPHYCONTROL1_ADDR 0xB8149004
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#define USBPHYCONTROL1_FSEL_SHIFT 2
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#define USBPHYCONTROL1_FSEL_MASK 0x1C
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#define USBPHYSTRAPCTRL_ADDR 0xB8149010
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#define USBPHYSTRAPCTRL_REFCLKSEL_SHIFT 4
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#define USBPHYSTRAPCTRL_REFCLKSEL_MASK 0x30
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#define USBPHYSTATUS_ADDR 0xB8149014
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#define USBPHYSTATUS_RX_PHY_CLK_MASK 0x200
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#define USBPHYSTATUS_RX_UTMI_CLK_MASK 0x100
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#define USBPHYSTATUS_VBUS_FAULT_MASK 0x80
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/* Definitions for UART0/1 setup */
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#define UART0CLKINTERNAL_CTRL_ADDR 0xB8144234
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#define UART0CLKINTERNAL_MASK 0x00000007
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#define UART0CLKOUT_CTRL_ADDR 0xB8144238
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#define UART0CLKOUT_MASK 0x000003FF
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#define UART1CLKINTERNAL_CTRL_ADDR 0xB814423C
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#define UART1CLKINTERNAL_MASK 0x00000007
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#define UART1CLKOUT_CTRL_ADDR 0xB8144240
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#define UART1CLKOUT_MASK 0x000003FF
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/* Definitions for timeout values */
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#define PLL_TIMEOUT_VALUE_US 20000
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#define USB_TIMEOUT_VALUE_US 200000
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#define SYS_CLK_LOCK_DELAY 3
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struct pll_parameters {
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u32 external_bypass_mask;
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u32 ctrl_addr;
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u32 internal_bypass_mask;
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u32 power_down_ctrl_addr;
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u32 power_down_ctrl_mask;
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u32 postdiv_addr;
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u32 postdiv1_shift;
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u32 postdiv1_mask;
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u32 postdiv2_shift;
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u32 postdiv2_mask;
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u32 status_addr;
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u32 status_lock_mask;
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u32 refdivider;
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u32 refdiv_addr;
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u32 refdiv_shift;
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u32 refdiv_mask;
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u32 feedback;
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u32 feedback_addr;
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u32 feedback_shift;
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u32 feedback_mask;
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};
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enum plls {
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SYS_PLL = 0,
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MIPS_PLL = 1
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};
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static struct pll_parameters pll_params[] = {
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[SYS_PLL] = {
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.external_bypass_mask = SYS_EXTERN_PLL_BYPASS_MASK,
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.ctrl_addr = SYS_PLL_CTRL4_ADDR,
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.internal_bypass_mask = SYS_INTERNAL_PLL_BYPASS_MASK,
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.power_down_ctrl_addr = SYS_PLL_PD_CTRL_ADDR,
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.power_down_ctrl_mask = SYS_PLL_PD_CTRL_PD_MASK,
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.postdiv_addr = SYS_PLL_POSTDIV_ADDR,
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.postdiv1_shift = SYS_PLL_POSTDIV1_SHIFT,
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.postdiv1_mask = SYS_PLL_POSTDIV1_MASK,
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.postdiv2_shift = SYS_PLL_POSTDIV2_SHIFT,
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.postdiv2_mask = SYS_PLL_POSTDIV2_MASK,
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.status_addr = SYS_PLL_STATUS_ADDR,
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.status_lock_mask = SYS_PLL_STATUS_LOCK_MASK,
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.refdivider = 0, /* Not defined yet */
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.refdiv_addr = 0, /* Not necessary */
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.refdiv_shift = 0, /* Not necessary */
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.refdiv_mask = 0, /* Not necessary */
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.feedback = 0, /* Not necessary */
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.feedback_addr = 0, /* Not necessary */
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.feedback_shift = 0, /* Not necessary */
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.feedback_mask = 0, /* Not necessary */
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},
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[MIPS_PLL] = {
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.external_bypass_mask = MIPS_EXTERN_PLL_BYPASS_MASK,
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.ctrl_addr = MIPS_PLL_CTRL2_ADDR,
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.internal_bypass_mask = MIPS_INTERNAL_PLL_BYPASS_MASK,
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.power_down_ctrl_addr = MIPS_PLL_PD_CTRL_ADDR,
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.power_down_ctrl_mask = MIPS_PLL_PD_CTRL_PD_MASK,
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.postdiv_addr = MIPS_PLL_POSTDIV_ADDR,
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.postdiv1_shift = MIPS_PLL_POSTDIV1_SHIFT,
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.postdiv1_mask = MIPS_PLL_POSTDIV1_MASK,
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.postdiv2_shift = MIPS_PLL_POSTDIV2_SHIFT,
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.postdiv2_mask = MIPS_PLL_POSTDIV2_MASK,
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.status_addr = MIPS_PLL_STATUS_ADDR,
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.status_lock_mask = MIPS_PLL_STATUS_LOCK_MASK,
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.refdivider = 0, /* Not defined yet */
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.refdiv_addr = MIPS_REFDIV_ADDR,
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.refdiv_shift = MIPS_REFDIV_SHIFT,
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.refdiv_mask = MIPS_REFDIV_MASK,
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.feedback = 0, /* Not defined yet */
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.feedback_addr = MIPS_FEEDBACK_ADDR,
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.feedback_shift = MIPS_FEEDBACK_SHIFT,
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.feedback_mask = MIPS_FEEDBACK_MASK
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}
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};
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static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2)
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{
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u32 reg;
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struct stopwatch sw;
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/* Check input parameters */
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assert(!(divider1 & ~(param->postdiv1_mask)));
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assert(!(divider2 & ~(param->postdiv2_mask)));
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/* Temporary bypass PLL (select XTAL as clock input) */
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reg = read32(PISTACHIO_CLOCK_SWITCH);
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reg &= ~(param->external_bypass_mask);
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write32(PISTACHIO_CLOCK_SWITCH, reg);
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/* Un-bypass PLL's internal bypass */
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reg = read32(param->ctrl_addr);
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reg &= ~(param->internal_bypass_mask);
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write32(param->ctrl_addr, reg);
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/* Disable power down */
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reg = read32(param->power_down_ctrl_addr);
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reg &= ~(param->power_down_ctrl_mask);
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write32(param->power_down_ctrl_addr, reg);
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if (param->feedback_addr) {
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assert(!(param->feedback & ~(param->feedback_mask)));
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reg = read32(param->feedback_addr);
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reg &= ~(param->feedback_mask);
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reg |= (param->feedback << param->feedback_shift) &
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param->feedback_mask;
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write32(param->feedback_addr, reg);
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}
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if (param->refdiv_addr) {
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assert(!(param->refdivider & ~(param->refdiv_mask)));
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reg = read32(param->refdiv_addr);
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reg &= ~(param->refdiv_mask);
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reg |= (param->refdivider << param->refdiv_shift) &
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param->refdiv_mask;
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write32(param->refdiv_addr, reg);
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}
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/* Read postdivider register value */
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reg = read32(param->postdiv_addr);
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/* Set divider 1 */
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reg &= ~(param->postdiv1_mask);
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reg |= (divider1 << param->postdiv1_shift) &
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param->postdiv1_mask;
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/* Set divider 2 */
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reg &= ~(param->postdiv2_mask);
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reg |= (divider2 << param->postdiv2_shift) &
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param->postdiv2_mask;
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/* Write back to register */
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write32(param->postdiv_addr, reg);
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/* Waiting for PLL to lock*/
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stopwatch_init_usecs_expire(&sw, PLL_TIMEOUT_VALUE_US);
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while (!(read32(param->status_addr) & param->status_lock_mask)) {
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if (stopwatch_expired(&sw))
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return PLL_TIMEOUT;
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}
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/* Start using PLL */
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reg = read32(PISTACHIO_CLOCK_SWITCH);
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reg |= param->external_bypass_mask;
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write32(PISTACHIO_CLOCK_SWITCH, reg);
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return CLOCKS_OK;
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}
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int sys_pll_setup(u8 divider1, u8 divider2)
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{
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return pll_setup(&(pll_params[SYS_PLL]), divider1, divider2);
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}
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int mips_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback)
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{
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pll_params[MIPS_PLL].refdivider = refdivider;
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pll_params[MIPS_PLL].feedback = feedback;
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return pll_setup(&(pll_params[MIPS_PLL]), divider1, divider2);
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}
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|
||||
/*
|
||||
* uart1_clk_setup: sets up clocks for UART1
|
||||
* divider1: 3-bit divider value
|
||||
* divider2: 10-bit divider value
|
||||
*/
|
||||
void uart1_clk_setup(u8 divider1, u16 divider2)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/* Check input parameters */
|
||||
assert(!(divider1 & ~(UART1CLKINTERNAL_MASK)));
|
||||
assert(!(divider2 & ~(UART1CLKOUT_MASK)));
|
||||
|
||||
/* Set divider 1 */
|
||||
reg = read32(UART1CLKINTERNAL_CTRL_ADDR);
|
||||
reg &= ~UART1CLKINTERNAL_MASK;
|
||||
reg |= divider1 & UART1CLKINTERNAL_MASK;
|
||||
write32(UART1CLKINTERNAL_CTRL_ADDR, reg);
|
||||
|
||||
/* Set divider 2 */
|
||||
reg = read32(UART1CLKOUT_CTRL_ADDR);
|
||||
reg &= ~UART1CLKOUT_MASK;
|
||||
reg |= divider2 & UART1CLKOUT_MASK;
|
||||
write32(UART1CLKOUT_CTRL_ADDR, reg);
|
||||
}
|
||||
|
||||
/* system_clk_setup: sets up the system (peripheral) clock */
|
||||
void system_clk_setup(u8 divider)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/* Check input parameters */
|
||||
assert(!(divider & ~(SYSCLKINTERNAL_MASK)));
|
||||
|
||||
/* Set system clock divider */
|
||||
reg = read32(SYSCLKINTERNAL_CTRL_ADDR);
|
||||
reg &= ~SYSCLKINTERNAL_MASK;
|
||||
reg |= divider & SYSCLKINTERNAL_MASK;
|
||||
write32(SYSCLKINTERNAL_CTRL_ADDR, reg);
|
||||
|
||||
/* Small delay to cover a maximum lock time of 1500 cycles */
|
||||
udelay(SYS_CLK_LOCK_DELAY);
|
||||
}
|
||||
|
||||
/* usb_clk_setup: sets up USB clock */
|
||||
int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel)
|
||||
{
|
||||
u32 reg;
|
||||
struct stopwatch sw;
|
||||
|
||||
/* Check input parameters */
|
||||
assert(!(divider & ~(USBPHYCLKOUT_MASK)));
|
||||
assert(!(refclksel & ~(USBPHYSTRAPCTRL_REFCLKSEL_MASK)));
|
||||
assert(!(fsel & ~(USBPHYCONTROL1_FSEL_MASK)));
|
||||
|
||||
/* Set USB divider */
|
||||
reg = read32(USBPHYCLKOUT_CTRL_ADDR);
|
||||
reg &= ~USBPHYCLKOUT_MASK;
|
||||
reg |= divider & USBPHYCLKOUT_MASK;
|
||||
write32(USBPHYCLKOUT_CTRL_ADDR, reg);
|
||||
|
||||
/* Set REFCLKSEL */
|
||||
reg = read32(USBPHYSTRAPCTRL_ADDR);
|
||||
reg &= ~USBPHYSTRAPCTRL_REFCLKSEL_MASK;
|
||||
reg |= (refclksel << USBPHYSTRAPCTRL_REFCLKSEL_SHIFT) &
|
||||
USBPHYSTRAPCTRL_REFCLKSEL_MASK;
|
||||
write32(USBPHYSTRAPCTRL_ADDR, reg);
|
||||
|
||||
/* Set FSEL */
|
||||
reg = read32(USBPHYCONTROL1_ADDR);
|
||||
reg &= ~USBPHYCONTROL1_FSEL_MASK;
|
||||
reg |= (fsel << USBPHYCONTROL1_FSEL_SHIFT) &
|
||||
USBPHYCONTROL1_FSEL_MASK;
|
||||
write32(USBPHYCONTROL1_ADDR, reg);
|
||||
|
||||
/* Waiting for USB clock status */
|
||||
stopwatch_init_usecs_expire(&sw, USB_TIMEOUT_VALUE_US);
|
||||
while (1) {
|
||||
reg = read32(USBPHYSTATUS_ADDR);
|
||||
if (reg & USBPHYSTATUS_VBUS_FAULT_MASK)
|
||||
return USB_VBUS_FAULT;
|
||||
if (stopwatch_expired(&sw))
|
||||
return USB_TIMEOUT;
|
||||
}
|
||||
|
||||
return CLOCKS_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SOC_IMGTEC_PISTACHIO_CLOCKS_H__
|
||||
#define __SOC_IMGTEC_PISTACHIO_CLOCKS_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Functions for PLL setting */
|
||||
int sys_pll_setup(u8 divider1, u8 divider2);
|
||||
int mips_pll_setup(u8 divider1, u8 divider2i, u8 predivider, u32 feedback);
|
||||
|
||||
/* Peripheral divider setting */
|
||||
void uart1_clk_setup(u8 divider1, u16 divider2);
|
||||
void system_clk_setup(u8 divider);
|
||||
int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel);
|
||||
|
||||
enum {
|
||||
CLOCKS_OK = 0,
|
||||
PLL_TIMEOUT = -1,
|
||||
USB_TIMEOUT = -2,
|
||||
USB_VBUS_FAULT = -3
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue