b3f666b252
Set elements: - UART1 clock dividers and MFIOs - SPIM1 clock dividers and MFIOs - USB clock dividers - System clock divider - System PLL - MIPS CPU PLL BUG=chrome-os-partner:31438 TEST=tested on Pisachio bring up board; UART, SPI NOR, SPI NAND, and USB have proper functionality. BRANCH=none Change-Id: Ib01186a652fd59295a4cafc3ca99b94aa9564f74 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 65e68d82f34bb40ef3cfb397ecf5df0c83201151 Original-Change-Id: Ia2c31bbbfc020dc4fd71c72b877414adfdfc42a8 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241423 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
55 lines
1.3 KiB
Text
55 lines
1.3 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2014 Imagination Technologies
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; version 2 of
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# the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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if BOARD_GOOGLE_URARA
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_512
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select BOOTBLOCK_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select CONFIG_SPI_FLASH_WINBOND
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select CPU_IMGTEC_PISTACHIO
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select COMMON_CBFS_SPI_WRAPPER
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select MAINBOARD_HAS_BOOTBLOCK_INIT
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select SPI_FLASH
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config MAINBOARD_DIR
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string
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default "google/urara"
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config MAINBOARD_PART_NUMBER
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string
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default "ImgTec Pistachio Virtual Platform"
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config BOOTBLOCK_MAINBOARD_INIT
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string
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default "mainboard/google/urara/bootblock.c"
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config DRAM_SIZE_MB
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int
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default 256
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config TTYS0_LCS
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int
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default 3
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endif
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