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mb/google/octopus: Enable wake-over-wifi for octopus variants 

This change enables wake-over-wifi functionality for all octopus
variants by making the following changeS:

1. Configure GPIO_119 as SCI active-low
2. Update GPE0_DW1 to include the group that GPIO_119 falls under
3. Add wake property to wifi device

BUG=b:77224247
TEST=Verified that wake-over-wifi works on yorp.

Change-Id: Ibae199c43e4d96da4c2f68f71a849c2f23d3e7b9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2018-06-04 17:10:31 -07:00
parent 2c373d6989
commit b41ae259d9
4 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
View File

@ -29,7 +29,7 @@ chip soc/intel/apollolake
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_NW_63_32"
register "gpe0_dw1" = "PMC_GPE_N_63_32"
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_NW_31_0"
@ -117,6 +117,7 @@ chip soc/intel/apollolake
device pci 12.0 off end # - SATA
device pci 13.0 on
chip drivers/intel/wifi
register "wake" = "GPE0_DW1_11"
device pci 00.0 on end
end
end # - PCIe-A 0 Onboard M2 Slot(Wifi)

3
src/mainboard/google/octopus/variants/baseboard/gpio.c
View File

@ -166,8 +166,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */
PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */
//TODO Reef uses PCIE_WAKE0 as GPI_SCI. Whats the difference?
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE3_B */
PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */
/* PCIE_CLKREQ[0:3]_B */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/

3
src/mainboard/google/octopus/variants/bip/devicetree.cb
View File

@ -29,7 +29,7 @@ chip soc/intel/apollolake
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_NW_63_32"
register "gpe0_dw1" = "PMC_GPE_N_63_32"
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_NW_31_0"
@ -117,6 +117,7 @@ chip soc/intel/apollolake
device pci 12.0 off end # - SATA
device pci 13.0 on
chip drivers/intel/wifi
register "wake" = "GPE0_DW1_11"
device pci 00.0 on end
end
end # - PCIe-A 0 Onboard M2 Slot(Wifi)

3
src/mainboard/google/octopus/variants/bip/gpio.c
View File

@ -164,8 +164,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */
PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */
//TODO Reef uses PCIE_WAKE0 as GPI_SCI. Whats the difference?
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE3_B */
PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */
/* PCIE_CLKREQ[0:3]_B */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/