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soc/cavium/cn81xx: Use write{32,64}p() 

Change-Id: I9c94f45264f541ce0849a53245534a10aaa5d854
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Elyes Haouas 2022-12-11 10:08:34 +01:00 committed by Felix Held
parent eb99f62456
commit b433470b02
1 changed files with 2 additions and 2 deletions
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4
src/soc/cavium/cn81xx/cpu.c
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@ -72,7 +72,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id))
return 1; return 1;
/* Write the address of the main entry point */ /* Write the address of the main entry point */
write64((void *)MIO_BOOT_AP_JUMP, (uintptr_t)secondary_init); write64p(MIO_BOOT_AP_JUMP, (uintptr_t)secondary_init);
/* Get coremask of cores in reset */ /* Get coremask of cores in reset */
const uint64_t reset = read64p(RST_PP_RESET); const uint64_t reset = read64p(RST_PP_RESET);
@ -86,7 +86,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id))
printk(BIOS_DEBUG, "CPU: Taking core %zu out of reset.\n", cpu); printk(BIOS_DEBUG, "CPU: Taking core %zu out of reset.\n", cpu);
/* Release core from reset */ /* Release core from reset */
write64((void *)RST_PP_RESET, reset & ~coremask); write64p(RST_PP_RESET, reset & ~coremask);
/* Wait for cores to finish coming out of reset */ /* Wait for cores to finish coming out of reset */
udelay(1); udelay(1);