intel/skylake: Add support for Gfx PEIM (AKA GOP)
This patch implements the igd_opregion using the write_acpi_tables mechanism to support GOP usage. BRANCH=none BUG=chrome-os-partner:44559 TEST=W/o GOP_SUPPORT in config, Built and boot on kunimitsu/glados. W/ GOP_SUPPORT enabled, build and boot on kunimitsu/glados, but on glados Dev screen can not be seen (OS display is fine). CQ-DEPEND=CL:303539 Change-Id: I4cd63dfe0d3f456c5f084e38db976425143f79e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4db57463a69c6114b1e2ed4035d378ee3a82783f Original-Change-Id: I6f3c29c1b608eeaad8f2bf79d17394d49f8e412c Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303387 Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12142 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
robbie zhang
Patrick Georgi
parent
32074149f7
commit
b45dde0b78
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@ -21,6 +21,7 @@
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <arch/cpu.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/smp/mpspec.h>
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@ -29,14 +30,10 @@
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#include <console/console.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/smm.h>
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#include <types.h>
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#include <string.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/intel/turbo.h>
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#include <ec/google/chromeec/ec.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <soc/intel/common/acpi.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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@ -45,6 +42,9 @@
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <string.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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/*
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* List of suported C-states in this processor.
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@ -541,8 +541,6 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
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return current;
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}
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#define ALIGN_CURRENT current = (ALIGN(current, 16))
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unsigned long southcluster_write_acpi_tables(device_t device,
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unsigned long current,
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struct acpi_rsdp *rsdp)
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@ -552,16 +550,6 @@ unsigned long southcluster_write_acpi_tables(device_t device,
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current = acpi_write_hpet(device, current, rsdp);
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ALIGN_CURRENT;
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#if CONFIG_GOP_SUPPORT
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igd_opregion_t *opregion;
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printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
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opregion = (igd_opregion_t *)current;
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init_igd_opregion(opregion);
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current += sizeof(igd_opregion_t);
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ALIGN_CURRENT;
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#endif
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ssdt2 = (acpi_header_t *)current;
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memset(ssdt2, 0, sizeof(acpi_header_t));
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if (ssdt2->length) {
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@ -27,6 +27,8 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <fsp/gop.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/pm.h>
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#include <soc/ramstage.h>
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@ -64,6 +66,9 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
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static void igd_init(struct device *dev)
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{
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if (IS_ENABLED(CONFIG_GOP_SUPPORT))
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return;
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/* IGD needs to be Bus Master */
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u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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@ -102,12 +107,93 @@ static void igd_init(struct device *dev)
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#endif
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}
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/* Initialize IGD OpRegion, called from ACPI code */
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static int init_igd_opregion(igd_opregion_t *opregion)
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{
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const optionrom_vbt_t *vbt;
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uint32_t vbt_len;
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u16 reg16;
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memset(opregion, 0, sizeof(igd_opregion_t));
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/* Read VBT table from flash */
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vbt = fsp_get_vbt(&vbt_len);
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if (!vbt)
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die("vbt data not found");
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memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
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sizeof(IGD_OPREGION_SIGNATURE));
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
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sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
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sizeof(opregion->vbt.gvd1));
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/* Size, in KB, of the entire OpRegion structure (including header)*/
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opregion->header.size = sizeof(igd_opregion_t) / KiB;
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opregion->header.version = IGD_OPREGION_VERSION;
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/* We just assume we're mobile for now */
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opregion->header.mailboxes = MAILBOXES_MOBILE;
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/* TODO Initialize Mailbox 1 */
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/* Initialize Mailbox 3 */
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opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
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opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
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opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
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opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
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opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
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opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
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opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
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opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
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opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
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opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
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opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
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opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
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opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
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opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
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opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
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/* TODO This may need to happen in S3 resume */
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pci_write_config32(SA_DEV_IGD, ASLS, (u32)opregion);
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reg16 = pci_read_config16(SA_DEV_IGD, SWSCI);
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reg16 &= ~GSSCIE;
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reg16 |= SMISCISEL;
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pci_write_config16(SA_DEV_IGD, SWSCI, reg16);
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return 0;
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}
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static unsigned long write_acpi_igd_opregion(device_t device,
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unsigned long current, struct acpi_rsdp *rsdp)
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{
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igd_opregion_t *opregion;
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/* If GOP is not used, exit here */
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if (!IS_ENABLED(CONFIG_GOP_SUPPORT))
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return current;
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/* If IGD is disabled, exit here */
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if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)
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return current;
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printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
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opregion = (igd_opregion_t *)current;
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init_igd_opregion(opregion);
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current += sizeof(igd_opregion_t);
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ALIGN_CURRENT;
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printk(BIOS_DEBUG, "current = %lx\n", current);
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return current;
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}
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static struct device_operations igd_ops = {
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.read_resources = &pci_dev_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.init = &igd_init,
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.ops_pci = &soc_pci_ops,
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.write_acpi_tables = write_acpi_igd_opregion,
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};
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static const unsigned short pci_device_ids[] = {
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@ -30,6 +30,8 @@
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_BUSMASTER 10
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#define ALIGN_CURRENT current = (ALIGN(current, 16))
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void acpi_fill_in_fadt(acpi_fadt_t *fadt);
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unsigned long acpi_madt_irq_overrides(unsigned long current);
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void acpi_mainboard_gnvs(global_nvs_t *gnvs);
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