mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVP
This patch adds UART0 config in early GPIO table Branch=None Test=Build coreboot and boot on ADLRVP-M board. Check UART logs Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52201 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,7 +13,17 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPP_A8, 1, DEEP),
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};
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static const struct pad_config early_uart_gpio_table[] = {
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/* UART0 RX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* UART0 TX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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};
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void variant_configure_early_gpio_pads(void)
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{
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if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
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gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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