mainboard/google: Rework Hatch so that SPD in CBFS is optional

All Hatch variants so far embed static SPD data encoded within the
firmware image. However we wish the flexibility for romstage
implementations that allow for reading the SPD data dynamically over
SMBus.

BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Edward O'Callaghan 2019-10-23 00:28:39 +11:00 committed by Patrick Georgi
parent fb2a9d5ed8
commit b4741616ea
3 changed files with 6 additions and 2 deletions

View File

@ -58,6 +58,10 @@ config DIMM_SPD_SIZE
int
default 512
config ROMSTAGE_SPD_CBFS
bool
default y
config DRIVER_TPM_SPI_BUS
default 0x1

View File

@ -20,7 +20,7 @@ ramstage-y += ramstage.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-y += romstage.c
romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
@ -33,4 +33,4 @@ VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
subdirs-y += spd
subdirs-$(CONFIG_ROMSTAGE_SPD_CBFS) += spd