cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e
(Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
parent
c51df93ccf
commit
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@ -516,10 +516,6 @@ config IOAPIC
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bool
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default n
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x0
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config USE_WATCHDOG_ON_BOOT
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bool
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default n
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@ -103,15 +103,6 @@ config VIRTUAL_ROM_SIZE
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the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
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size is 16 MB.
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config CACHE_ROM_SIZE_OVERRIDE
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hex "Cache ROM Size"
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default CBFS_SIZE
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help
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This is the size of the cachable area that is passed into the FSP in
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the early initialization. Typically this should be the size of the CBFS
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area, but the size must be a power of 2 whereas the CBFS size does not
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have this limitation.
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config USE_GENERIC_FSP_CAR_INC
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bool
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default n
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@ -118,12 +118,15 @@ static inline unsigned int fls(unsigned int x)
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}
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#endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */
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/* Align up to next power of 2, suitable for ROMCC and assembler too.
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* Range of result 256kB to 128MB is good enough here.
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*/
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/* Align up/down to next power of 2, suitable for ROMCC and assembler
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too. Range of result 256kB to 128MB is good enough here. */
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#define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \
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(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
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#define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
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#define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x))
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/* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */
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#define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12)
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/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set
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* as write-back cacheable to speed up ramstage decompression.
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@ -135,29 +138,29 @@ static inline unsigned int fls(unsigned int x)
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# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
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#endif
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/* Select CACHE_ROM_SIZE to use with MTRR setup. For most cases this
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* resolves to a suitable CONFIG_ROM_SIZE but some odd cases need to
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* use CONFIG_CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig.
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*/
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#if (CONFIG_CACHE_ROM_SIZE_OVERRIDE != 0)
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# define CACHE_ROM_SIZE CONFIG_CACHE_ROM_SIZE_OVERRIDE
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/* For ROM caching, generally, try to use the next power of 2. */
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#define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
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#define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE)
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#if (OPTIMAL_CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || \
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(OPTIMAL_CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE))
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# error "Optimal CACHE_ROM_SIZE can't be derived, _POW2_MASK needs refinement."
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#endif
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/* Make sure it doesn't overlap CAR, though. If the gap between
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CAR and 4GiB is too small, make it at most the size of this
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gap. As we can't align up (might overlap again), align down
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to get a power of 2 again, for a single MTRR. */
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#define CAR_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
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#if CAR_END > OPTIMAL_CACHE_ROM_BASE
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# define CACHE_ROM_SIZE _ALIGN_DOWN_POW2(_FROM_4G_TOP(CAR_END))
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#else
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# if ((CONFIG_ROM_SIZE & (CONFIG_ROM_SIZE-1)) == 0)
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# define CACHE_ROM_SIZE CONFIG_ROM_SIZE
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# else
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# define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
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# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \
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(2 * CONFIG_ROM_SIZE))
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# error "CACHE_ROM_SIZE is not optimal."
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# endif
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# endif
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# define CACHE_ROM_SIZE OPTIMAL_CACHE_ROM_SIZE
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#endif
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#if ((CACHE_ROM_SIZE & (CACHE_ROM_SIZE - 1)) != 0)
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# error "CACHE_ROM_SIZE is not a power of 2, _POW2_MASK needs refinement."
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#endif
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#if ((CACHE_ROM_SIZE & (CACHE_ROM_SIZE-1)) != 0)
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# error "CACHE_ROM_SIZE is not a power of 2."
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#endif
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#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
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#define CACHE_ROM_BASE _FROM_4G_TOP(CACHE_ROM_SIZE)
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#if (IS_ENABLED(CONFIG_SOC_SETS_MSRS) && !defined(__ASSEMBLER__) \
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&& !defined(__ROMCC__))
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@ -37,10 +37,6 @@ config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_FILE
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string
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default "../intel/fsp/rangeley/FvFsp.bin"
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@ -36,10 +36,6 @@ config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_FILE
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string
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default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
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@ -38,10 +38,6 @@ config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_FILE
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string
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default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP
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@ -23,10 +23,6 @@ config IRQ_SLOT_COUNT
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int
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default 18
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config CBFS_SIZE
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hex
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default 0x00200000
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@ -36,10 +36,6 @@ config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_FILE
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string
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default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
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@ -37,10 +37,6 @@ config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_FILE
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string
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default "../intel/fsp/rangeley/FvFsp.bin"
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@ -23,10 +23,6 @@ config IRQ_SLOT_COUNT
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int
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default 18
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config CBFS_SIZE
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hex
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default 0x00200000
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@ -24,10 +24,6 @@ config IRQ_SLOT_COUNT
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int
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default 18
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config CBFS_SIZE
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hex
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default 0x00200000
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@ -27,10 +27,6 @@ config IRQ_SLOT_COUNT
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int
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default 18
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x1000000
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config CBFS_SIZE
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hex
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default 0x00D00000
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@ -44,10 +44,6 @@ config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x1000000
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config CBFS_SIZE
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hex
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default 0x00e00000
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