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siemens/mc_apl4: Provide CLK on APL Pin PMU_SUSCLK

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This patch provides a clock on Pin PMU_SUSCLK. This is necessary for correct
function of the SMARC module.

Test=mc_apl4 flashed, booted into Linux, ckecked CLK with scope

Change-Id: Ieb1d66b5a09363c9bed2b19e7a204f206ee04158
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32168
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Uwe Poeche 2019-04-02 09:18:53 +02:00 committed by Patrick Georgi
parent 2e2fe3cc91
commit b4a4036306
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c
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@ -131,7 +131,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(PMU_SLP_S0_B, UP_20K, DEEP),
PAD_CFG_GPI(PMU_SLP_S3_B, UP_20K, DEEP),
PAD_CFG_GPI(PMU_SLP_S4_B, UP_20K, DEEP),
PAD_CFG_GPI(PMU_SUSCLK, DN_20K, DEEP),
PAD_CFG_GPI(PMU_WAKE_B, DN_20K, DEEP),
PAD_CFG_GPI(SUS_STAT_B, DN_20K, DEEP),
PAD_CFG_GPI(SUSPWRDNACK, DN_20K, DEEP),
@ -380,6 +379,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPIO_43, UP_20K, DEEP, NF1), /* LPSS_UART1_TXD */
PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */
PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1),/* 32,78 kHz used on SMARC */
};
const struct pad_config *variant_early_gpio_table(size_t *num)