src/soc/intel/cannonlake: Bump MAX_CPU from 8->12
This impacts boards: hatch (&variants) and drallion. Some variants like Puff can have up to 12 cores. coreboot should take the min() where MAX_CPU is the upper bound. Further to that, boards themseleves shouldn't be setting the MAX_CPUS, the chipset should be and so do that. BRANCH=none BUG=b:146255011 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I284d027886f662ebb8414ea92540916ed19bc797 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
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@ -71,10 +71,6 @@ config MAINBOARD_PART_NUMBER
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string
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default "Drallion" if BOARD_GOOGLE_DRALLION
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config MAX_CPUS
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int
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default 8
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config UART_FOR_CONSOLE
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int
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default 0 if BOARD_GOOGLE_DRALLION
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@ -98,10 +98,6 @@ config MAINBOARD_PART_NUMBER
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default "Puff" if BOARD_GOOGLE_PUFF
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default "Stryke" if BOARD_GOOGLE_STRYKE
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config MAX_CPUS
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int
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default 8
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config OVERRIDE_DEVICETREE
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string
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default "variants/helios_diskswap/overridetree.cb" if BOARD_GOOGLE_HELIOS_DISKSWAP
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@ -108,6 +108,10 @@ config CPU_SPECIFIC_OPTIONS
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select FSP_T_XIP if FSP_CAR
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select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
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config MAX_CPUS
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int
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default 12
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config DCACHE_RAM_BASE
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default 0xfef00000
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