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pcengines/apu1: Fix 0:15.x PCIe root ports 

Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done
to only advertise x1 lane width for PCIe link 0:15.0.

Hide functions of PCIe links that have no slots connected. Our PCI
infrastructure does not support bridge devices that are set off
in devicetree but remain visible in the PCI hardware tree.

Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8388
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki 2015-01-17 18:08:40 +02:00
parent 07354235df
commit b5a8a13bde
2 changed files with 3 additions and 3 deletions
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2
src/mainboard/pcengines/apu1/devicetree.cb
View File

@ -83,7 +83,7 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 15.3 off end # PCIe PortD
device pci 16.0 on end # OHCI USB 10-13
device pci 16.2 on end # EHCI USB 10-13
register "gpp_configuration" = "0"
register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
register "disconnect_pcib" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800

4
src/mainboard/pcengines/apu1/platform_cfg.h
View File

@ -185,7 +185,7 @@
* GPP_CFGMODE_X2110
* GPP_CFGMODE_X1111
*/
#define GPP_CFGMODE GPP_CFGMODE_X4000
#define GPP_CFGMODE GPP_CFGMODE_X1111
/**
* @def NB_SB_GEN2
@ -206,7 +206,7 @@
* TRUE - ports visible always, even port empty
* FALSE - ports invisible if port empty
*/
#define SB_GPP_UNHIDE_PORTS TRUE
#define SB_GPP_UNHIDE_PORTS FALSE
/**
* @def GEC_CONFIG