soc/amd/picasso/pci_gpp: Replace the swizzle string with a u8 array
I think it makes the code a bit cleaner. BUG=b:170595019 BRANCH=zork TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib5e8e5b690d9612e8ae257f5d15c25122e1c91e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -21,20 +21,20 @@
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struct pci_routing {
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unsigned int devfn;
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unsigned int group;
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const char intx[5];
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uint8_t pin[4];
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};
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/* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */
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static const struct pci_routing pci_routing_table[] = {
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{PCIE_GPP_0_DEVFN, 0, "ABCD"},
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{PCIE_GPP_1_DEVFN, 1, "ABCD"},
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{PCIE_GPP_2_DEVFN, 2, "ABCD"},
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{PCIE_GPP_3_DEVFN, 3, "ABCD"},
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{PCIE_GPP_4_DEVFN, 4, "ABCD"},
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{PCIE_GPP_5_DEVFN, 5, "ABCD"},
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{PCIE_GPP_6_DEVFN, 6, "ABCD"},
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{PCIE_GPP_A_DEVFN, 7, "ABCD"},
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{PCIE_GPP_B_DEVFN, 7, "CDAB"},
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{PCIE_GPP_0_DEVFN, 0, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
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{PCIE_GPP_1_DEVFN, 1, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
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{PCIE_GPP_2_DEVFN, 2, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
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{PCIE_GPP_3_DEVFN, 3, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
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{PCIE_GPP_4_DEVFN, 4, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
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{PCIE_GPP_5_DEVFN, 5, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
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{PCIE_GPP_6_DEVFN, 6, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
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{PCIE_GPP_A_DEVFN, 7, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },
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{PCIE_GPP_B_DEVFN, 7, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} },
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};
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/*
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@ -71,7 +71,7 @@ static unsigned int calculate_irq(const struct pci_routing *pci_routing, unsigne
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{
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unsigned int irq_index;
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irq_index = pci_routing->group * 4;
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irq_index += pci_routing->intx[i] - 'A';
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irq_index += pci_routing->pin[i];
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return irq_index;
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}
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