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intel/skylake: Enable SkipMpInit token 

This patch helps to enable SkipMpInit token of FSP SiliconInit UPD

BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB.

CQ-DEPEND=CL:310869

Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577
Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310192
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12943
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Rizwan Qureshi 2015-11-19 16:27:03 +05:30 committed by Patrick Georgi
parent 19d9fe9ebc
commit b6319c1121
2 changed files with 3 additions and 0 deletions
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2
src/soc/intel/skylake/chip.c
View File

@ -345,6 +345,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode;
params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse;
params->SkipMpInit = config->SkipMpInit;
/* Show SPI controller if enabled in devicetree.cb */
dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;

1
src/soc/intel/skylake/chip.h
View File

@ -324,6 +324,7 @@ struct soc_intel_skylake_config {
* Values: 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2; PchSfpw8Clk.
*/
u8 SerialIrqConfigStartFramePulse;
u8 SkipMpInit;
};
typedef struct soc_intel_skylake_config config_t;