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mb/google/nissa/var/anraggar: Enable CNVi Bluetooth 

Intel CNVi WLAN's BT uses USB2 Port 10 inside the SOC,
and the relevant configuration needs to be modified in overridtre.cb.

BUG=b:304920262
TEST=lsusb
     ID 8087:0033 Intel Corp.
     rfkill list
     hci0:Bluetooth

Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79055
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Weimin Wu 2023-11-14 16:14:25 +08:00 committed by Felix Held
parent ae2f046484
commit b667e27952
2 changed files with 13 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/brya/variants/anraggar/gpio.c
View File

@ -9,6 +9,8 @@
static const struct pad_config override_gpio_table[] = { static const struct pad_config override_gpio_table[] = {
/* A7 : NC ==> LTE_Present */ /* A7 : NC ==> LTE_Present */
PAD_CFG_GPI(GPP_A7, NONE, DEEP), PAD_CFG_GPI(GPP_A7, NONE, DEEP),
/* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
PAD_CFG_GPO(GPP_A8, 1, DEEP),
/* A18 : NC ==> HDMI_HPD_SRC*/ /* A18 : NC ==> HDMI_HPD_SRC*/
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
@ -80,8 +82,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_F11, 1, DEEP), PAD_CFG_GPO(GPP_F11, 1, DEEP),
/* F12 : GSXDOUT ==> WWAN_RST_L */ /* F12 : GSXDOUT ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_F12, 0, DEEP), PAD_CFG_GPO(GPP_F12, 0, DEEP),
/* F16 : NC ==> WWAN_PWR_ENABLE */ /* D6 : NC ==> WWAN_PWR_ENABLE */
PAD_CFG_GPO(GPP_F16, 1, DEEP), PAD_CFG_GPO(GPP_D6, 1, DEEP),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),

11
src/mainboard/google/brya/variants/anraggar/overridetree.cb
View File

@ -409,7 +409,8 @@ chip soc/intel/alderlake
[3] = USB2_PORT_MID(OC_SKIP), /* Type-A DB (6.2 inch) */ [3] = USB2_PORT_MID(OC_SKIP), /* Type-A DB (6.2 inch) */
[4] = USB2_PORT_SHORT(OC_SKIP), /* LTE (3.3 inch) */ [4] = USB2_PORT_SHORT(OC_SKIP), /* LTE (3.3 inch) */
[5] = USB2_PORT_SHORT(OC_SKIP), /* UFC (3.7 inch) */ [5] = USB2_PORT_SHORT(OC_SKIP), /* UFC (3.7 inch) */
[7] = USB2_PORT_SHORT(OC_SKIP), /* BT (2.5 inch) */ [7] = USB2_PORT_SHORT(OC_SKIP), /* Bluetooth port for PCIe WLAN (2.5 inch) */
[9] = USB2_PORT_SHORT(OC_SKIP), /* Bluetooth port for CNVi WLAN */
}" }"
chip drivers/usb/acpi chip drivers/usb/acpi
device ref xhci_root_hub on device ref xhci_root_hub on
@ -452,11 +453,17 @@ chip soc/intel/alderlake
device ref usb2_port6 on end device ref usb2_port6 on end
end end
chip drivers/usb/acpi chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth"" register "desc" = ""PCIe Bluetooth""
register "type" = "UPC_TYPE_INTERNAL" register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port8 on end device ref usb2_port8 on end
end end
chip drivers/usb/acpi
register "desc" = ""CNVi Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port10 on end
end
chip drivers/usb/acpi chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "desc" = ""USB3 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_USB3_A" register "type" = "UPC_TYPE_USB3_A"