cpu/intel/model_2065x: Use parallel MP init
TESTED on Thinkpad X201 with a i7 CPU M620 CPU (hyperthread dual core). Boots ~28ms faster. Change-Id: I56b352f9d76ee58f5c82cd431a4e0fa206f848a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans
parent
548f33a9f4
commit
b66ee5507c
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@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS
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select TSC_SYNC_MFENCE
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select CPU_INTEL_COMMON
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select NO_FIXED_XIP_ROM_SIZE
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select PARALLEL_MP
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config BOOTBLOCK_CPU_INIT
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string
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@ -20,6 +20,7 @@
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/* Nehalem bus clock is fixed at 133MHz */
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#define NEHALEM_BCLK 133
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#define CORE_THREAD_COUNT_MSR 0x35
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#define MSR_FEATURE_CONFIG 0x13c
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#define MSR_FLEX_RATIO 0x194
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#define FLEX_RATIO_LOCK (1 << 20)
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/acpi.h>
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@ -22,6 +23,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/mp.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/intel/speedstep.h>
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#include <cpu/intel/turbo.h>
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@ -109,29 +111,6 @@ static acpi_cstate_t cstate_map[] = {
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{ 0 }
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};
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int cpu_get_apic_id_map(int *apic_id_map)
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{
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int i;
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struct cpuid_result result;
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unsigned int threads_per_package, threads_per_core;
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/* Logical processors (threads) per core */
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result = cpuid_ext(0xb, 0);
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threads_per_core = result.ebx & 0xffff;
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/* Logical processors (threads) per package */
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result = cpuid_ext(0xb, 1);
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threads_per_package = result.ebx & 0xffff;
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for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; ++i) {
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apic_id_map[i] = (i % threads_per_core)
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+ ((i / threads_per_core) << 2);
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}
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return threads_per_package;
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}
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int cpu_config_tdp_levels(void)
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{
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msr_t platform_info;
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@ -250,58 +229,6 @@ static void configure_mca(void)
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wrmsr(IA32_MC0_STATUS + (i * 4), msr);
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}
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/*
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* Initialize any extra cores/threads in this package.
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*/
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static void intel_cores_init(struct device *cpu)
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{
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struct cpuid_result result;
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unsigned int threads_per_package, threads_per_core, i;
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/* Logical processors (threads) per core */
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result = cpuid_ext(0xb, 0);
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threads_per_core = result.ebx & 0xffff;
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/* Logical processors (threads) per package */
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result = cpuid_ext(0xb, 1);
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threads_per_package = result.ebx & 0xffff;
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/* Only initialize extra cores from BSP */
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if (cpu->path.apic.apic_id)
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return;
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printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n",
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cpu->path.apic.apic_id, threads_per_package/threads_per_core,
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threads_per_core);
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for (i = 1; i < threads_per_package; ++i) {
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struct device_path cpu_path;
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struct device *new;
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/* Build the CPU device path */
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cpu_path.type = DEVICE_PATH_APIC;
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cpu_path.apic.apic_id =
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cpu->path.apic.apic_id + (i % threads_per_core)
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+ ((i / threads_per_core) << 2);
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/* Allocate the new CPU device structure */
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new = alloc_dev(cpu->bus, &cpu_path);
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if (!new)
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continue;
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printk(BIOS_DEBUG, "CPU: %u has core %u\n",
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cpu->path.apic.apic_id,
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new->path.apic.apic_id);
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/* Start the new CPU */
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if (is_smp_boot() && !start_cpu(new)) {
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/* Record the error in cpu? */
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printk(BIOS_ERR, "CPU %u would not start!\n",
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new->path.apic.apic_id);
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}
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}
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}
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static void model_2065x_init(struct device *cpu)
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{
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char processor_name[49];
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@ -309,8 +236,6 @@ static void model_2065x_init(struct device *cpu)
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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intel_update_microcode_from_cbfs();
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/* Clear out pending MCEs */
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configure_mca();
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@ -320,10 +245,6 @@ static void model_2065x_init(struct device *cpu)
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printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid(),
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boot_cpu());
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/* Setup MTRRs based on physical address size */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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/* Setup Page Attribute Tables (PAT) */
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// TODO set up PAT
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@ -348,9 +269,75 @@ static void model_2065x_init(struct device *cpu)
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/* Enable Turbo */
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enable_turbo();
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}
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/* Start up extra cores */
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intel_cores_init(cpu);
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/* MP initialization support. */
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static const void *microcode_patch;
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static void pre_mp_init(void)
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{
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/* Setup MTRRs based on physical address size. */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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}
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static int get_cpu_count(void)
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{
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msr_t msr;
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int num_threads;
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int num_cores;
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msr = rdmsr(CORE_THREAD_COUNT_MSR);
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num_threads = (msr.lo >> 0) & 0xffff;
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num_cores = (msr.lo >> 16) & 0xffff;
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printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
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num_cores, num_threads);
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return num_threads;
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}
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static void get_microcode_info(const void **microcode, int *parallel)
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{
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microcode_patch = intel_microcode_find();
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*microcode = microcode_patch;
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*parallel = 1;
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}
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static void per_cpu_smm_trigger(void)
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{
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/* Relocate the SMM handler. */
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smm_relocate();
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/* After SMM relocation a 2nd microcode load is required. */
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intel_microcode_load_unlocked(microcode_patch);
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}
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static void post_mp_init(void)
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{
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/* Now that all APs have been relocated as well as the BSP let SMIs
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* start flowing. */
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southbridge_smm_init();
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/* Lock down the SMRAM space. */
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smm_lock();
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = smm_info,
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.get_microcode_info = get_microcode_info,
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.pre_mp_smm_init = smm_initialize,
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.per_cpu_smm_trigger = per_cpu_smm_trigger,
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.relocation_handler = smm_relocation_handler,
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.post_mp_init = post_mp_init,
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};
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void bsp_init_and_start_aps(struct bus *cpu_bus)
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{
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if (mp_init_with_smm(cpu_bus, &mp_ops))
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printk(BIOS_ERR, "MP initialization failure.\n");
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}
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static struct device_operations cpu_dev_ops = {
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@ -311,7 +311,7 @@ static const struct pci_driver mc_driver_44 __pci_driver = {
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static void cpu_bus_init(struct device *dev)
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{
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initialize_cpus(dev->link_list);
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bsp_init_and_start_aps(dev->link_list);
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}
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static struct device_operations cpu_bus_ops = {
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