util/mb/google/tmpl/puff: Import overridetree.cb copy
BUG=b:154071868 BRANCH=none TEST=none Change-Id: I40faa5f80e78cd73ba5ef977574f7f662c0ab8a1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This commit is contained in:
Edward O'Callaghan
Edward O'Callaghan
parent
7587526583
commit
b6737fc54a
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@ -1,6 +1,406 @@
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chip soc/intel/cannonlake
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# Enable heci communication
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register "HeciEnabled" = "1"
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# Auto-switch between X4 NVMe and X2 NVMe.
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register "TetonGlacierMode" = "1"
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexSPI0] = PchSerialIoPci,
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[PchSerialIoIndexSPI1] = PchSerialIoPci,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# USB configuration
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# NOTE: This only applies to Puff,
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# usb2_ports[1] and usb2_ports[3] were swapped on
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# reference schematics after Puff has been built.
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register "usb2_ports[0]" = "{
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.enable = 1,
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.ocpin = OC2,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 2
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
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register "usb2_ports[2]" = "{
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.enable = 1,
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.ocpin = OC3,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 3
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register "usb2_ports[3]" = "{
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.enable = 1,
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.ocpin = OC1,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 1
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register "usb2_ports[4]" = "{
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.enable = 1,
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.ocpin = OC_SKIP,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 4
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register "usb2_ports[5]" = "{
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.enable = 1,
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.ocpin = OC0,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A port 0
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register "usb2_ports[6]" = "USB2_PORT_EMPTY"
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register "usb2_ports[7]" = "USB2_PORT_EMPTY"
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register "usb2_ports[8]" = "USB2_PORT_EMPTY"
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register "usb2_ports[9]" = "{
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.enable = 1,
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.ocpin = OC_SKIP,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # BT
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
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# Enable eMMC HS400
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register "ScsEmmcHs400Enabled" = "1"
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# EMMC Tx CMD Delay
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# Refer to EDS-Vol2-14.3.7.
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# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-14.3.8.
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# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
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# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-14.3.9.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
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# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-14.3.10.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
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# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-14.3.12.
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# [17:16] stands for Rx Clock before Output Buffer,
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# 00: Rx clock after output buffer,
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# 01: Rx clock before output buffer,
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# 10: Automatic selection based on working mode.
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# 11: Reserved
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
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# EMMC Rx Strobe Delay
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# Refer to EDS-Vol2-14.3.11.
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# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
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# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
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# Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
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register "PchHdaAudioLinkSsp1" = "0"
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register "PchHdaAudioLinkDmic0" = "0"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| I2C0 | RFU |
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#| I2C2 | PS175 |
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#| I2C3 | MST |
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#| I2C4 | Audio |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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}"
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# PCIe port 7 for LAN
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register "PcieRpEnable[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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# PCIe port 11 (x2) for NVMe hybrid storage devices
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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# Uses CLK SRC 0
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register "PcieClkSrcUsage[0]" = "6"
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register "PcieClkSrcClkReq[0]" = "0"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "vSD3_CD_B"
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# SATA port 1 Gen3 Strength
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# Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
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register "sata_port[1].TxGen3DeEmphEnable" = "1"
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register "sata_port[1].TxGen3DeEmph" = "0x20"
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device domain 0 on
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device pci 14.0 on
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chip drivers/usb/acpi
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device usb 0.0 on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Front Left""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(0, 0)"
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device usb 2.0 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port Rear""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 3)"
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device usb 2.1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Front Right""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(0, 1)"
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device usb 2.2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Rear Right""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device usb 2.3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Rear Middle""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device usb 2.4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Rear Left""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 0)"
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device usb 2.5 on end
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end
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chip drivers/usb/acpi
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device usb 2.6 off end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Front Left""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(0, 0)"
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device usb 3.0 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Front Right""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(0, 1)"
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device usb 3.1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Rear Right""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device usb 3.2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Rear""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 3)"
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device usb 3.3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Rear Left""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 0)"
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device usb 3.4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Rear Middle""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device usb 3.5 on end
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end
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end
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end
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end # USB xHCI
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device pci 15.0 off
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# RFU - Reserved for Future Use.
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end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 on
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chip drivers/i2c/generic
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register "hid" = ""1AF80175""
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register "name" = ""PS17""
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register "desc" = ""Parade PS175""
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device i2c 4a on end
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end
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end # I2C #2, PCON PS175.
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device pci 15.3 on
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chip drivers/i2c/generic
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register "hid" = ""10EC2142""
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register "name" = ""RTD2""
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register "desc" = ""Realtek RTD2142""
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device i2c 4a on end
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end
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end # I2C #3, Realtek RTD2142.
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device pci 19.0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5682""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
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register "property_count" = "1"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end #I2C #4
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device pci 1a.0 on end # eMMC
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device pci 1c.6 on
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chip drivers/net
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register "customized_leds" = "0x05af"
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register "wake" = "GPE0_DW1_07" # GPP_C7
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)"
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register "stop_delay_ms" = "12" # NIC needs time to quiesce
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register "stop_off_delay_ms" = "1"
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register "has_power_resource" = "1"
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register "device_index" = "0"
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device pci 00.0 on end
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end
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end # RTL8111H Ethernet NIC
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device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
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device pci 1e.3 off end # GSPI #1
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end
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------+-------+
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#| Domain/Setting | SA | IA | GTUS | GTS |
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#+----------------+-------+-------+-------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 5A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
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#| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
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#+----------------+-------+-------+-------+-------+
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#Note: IccMax settings are moved to SoC code
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = 0,
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.voltage_limit = 1520,
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.ac_loadline = 1004,
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||||
.dc_loadline = 1004,
|
||||
}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = 0,
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.voltage_limit = 1520,
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.ac_loadline = 181,
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||||
.dc_loadline = 181,
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||||
}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
|
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 319,
|
||||
.dc_loadline = 319,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_SLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 319,
|
||||
.dc_loadline = 319,
|
||||
}"
|
||||
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in New Issue