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nb/intel/x4x: Sort code in program_dll() 

Move the last block of the sync DLL programming up. It's independent
of the switch/case statement that it's moved around.

Change-Id: I71bc1ca1c629e4f2f4a13474c7e2c22d1a3b65d9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber 2021-03-28 18:52:14 +02:00
parent 67d099a7f2
commit b6a2ebe5ef
1 changed files with 16 additions and 16 deletions
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32
src/northbridge/intel/x4x/raminit_ddr23.c
View File

@ -880,6 +880,22 @@ static void program_dll(struct sysinfo *s)
printk(BIOS_NOTICE, "HMC failed, using async mode\n");
}
mchbar_clrbits8(0x180, 1 << 7);
if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)
|| (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz
&& s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {
i = mchbar_read8(0x1c8) & 0xf;
if (s->spd_type == DDR2)
i = (i + 10) % 14;
else /* DDR3 */
i = (i + 3) % 12;
mchbar_clrsetbits8(0x1c8, 0x1f, i);
mchbar_setbits8(0x180, 1 << 4);
while (mchbar_read8(0x180) & (1 << 4))
;
}
switch (s->selected_timings.mem_clk) {
case MEM_CLOCK_667MHz:
clk = 0x1a;
@ -903,22 +919,6 @@ static void program_dll(struct sysinfo *s)
break;
}
mchbar_clrbits8(0x180, 1 << 7);
if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)
|| (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz
&& s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {
i = mchbar_read8(0x1c8) & 0xf;
if (s->spd_type == DDR2)
i = (i + 10) % 14;
else /* DDR3 */
i = (i + 3) % 12;
mchbar_clrsetbits8(0x1c8, 0x1f, i);
mchbar_setbits8(0x180, 1 << 4);
while (mchbar_read8(0x180) & (1 << 4))
;
}
reg8 = mchbar_read8(0x188) & ~1;
mchbar_write8(0x188, reg8);
reg8 &= ~0x3e;