arch/x86/include: Add #defines for IVRS tables
I/O Virtualization Reporting Structure (IVRS) definitions from: AMD I/O Virtualization Technology (IOMMU) Specification 48882—Rev 2.62—February 2015 Change-Id: I4809856eb922cbd9de4a2707cee78dba603af528 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16506 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* AMD I/O Virtualization Technology (IOMMU)
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* Specification 48882—Rev 2.62—February 2015
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*
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* from http://www.uefi.org/acpi
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* I/O Virtualization Reporting Structure (IVRS)
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*/
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#ifndef __ARCH_ACPI_IVRS_H
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#define __ARCH_ACPI_IVRS_H
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/* I/O Virtualization Reporting Structure (IVRS) */
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#define IVHD_BLOCK_TYPE_LEGACY__FIXED 0x10
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#define IVHD_BLOCK_TYPE_FULL__FIXED 0x11
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#define IVHD_BLOCK_TYPE_FULL__ACPI_HID 0x40
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/* IVRS Revision Field */
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#define IVRS_FORMAT_FIXED 0x01 /* Type 10h & 11h only */
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#define IVRS_FORMAT_MIXED 0x02 /* Type 10h, 11h, & 40h */
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/* IVRS IVinfo Field */
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/* ATS response address range reserved */
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#define IVINFO_HT_ATS_RESERVED (1 << 22)
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/* Virtual Address size - All other values are reserved */
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#define IVINFO_VA_SIZE_32_BITS (0x20 << 15)
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#define IVINFO_VA_SIZE_40_BITS (0x28 << 15)
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#define IVINFO_VA_SIZE_48_BITS (0x30 << 15)
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#define IVINFO_VA_SIZE_64_BITS (0x40 << 15)
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/* Physical Address size - All other values are reserved */
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#define IVINFO_PA_SIZE_40_BITS (0x28 << 8)
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#define IVINFO_PA_SIZE_48_BITS (0x30 << 8)
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#define IVINFO_PA_SIZE_52_BITS (0x34 << 8)
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/* Guest Virtual Address size - All other values are reserved */
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#define IVINFO_GVA_SIZE_48_BITS (0x02 << 5)
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/* Extended Feature Support */
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#define IVINFO_EFR_SUPPORTED 0x01
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/* IVHD Flags Field */
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#define IVHD_FLAG_PPE_SUP (1 << 7) /* Type 10h only */
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#define IVHD_FLAG_PREF_SUP (1 << 6) /* Type 10h only */
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#define IVHD_FLAG_COHERENT (1 << 5)
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#define IVHD_FLAG_IOTLB_SUP (1 << 4)
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#define IVHD_FLAG_ISOC (1 << 3)
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#define IVHD_FLAG_RES_PASS_PW (1 << 2)
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#define IVHD_FLAG_PASS_PW (1 << 1)
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#define IVHD_FLAG_HT_TUN_EN (1 << 0)
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/* IVHD IOMMU Info Field */
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#define IOMMU_INFO_UNIT_ID_SHIFT 8
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/* IVHD IOMMU Feature Reporting Field */
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#define IOMMU_FEATURE_HATS_SHIFT 30 /* Type 10h only */
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#define IOMMU_FEATURE_GATS_SHIFT 28 /* Type 10h only */
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#define IOMMU_FEATURE_MSI_NUM_PPR_SHIFT 23
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#define IOMMU_FEATURE_PN_BANKS_SHIFT 17
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#define IOMMU_FEATURE_PN_COUNTERS_SHIFT 13
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#define IOMMU_FEATURE_PA_SMAX_SHIFT 8 /* Type 10h only */
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#define IOMMU_FEATURE_HE_SUP (1 << 7) /* Type 10h only */
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#define IOMMU_FEATURE_GA_SUP (1 << 6) /* Type 10h only */
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#define IOMMU_FEATURE_IA_SUP (1 << 5) /* Type 10h only */
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#define IOMMU_FEATURE_GLX_SINGLE_LEVEL (0 << 3) /* Type 10h only */
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#define IOMMU_FEATURE_GLX_TWO_LEVEL (1 << 3) /* Type 10h only */
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#define IOMMU_FEATURE_GLX_THREE_LEVEL (2 << 3) /* Type 10h only */
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#define IOMMU_FEATURE_GT_SUP (1 << 1) /* Type 10h only */
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#define IOMMU_FEATURE_NX_SUP (1 << 0) /* Type 10h only */
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/* IVHD Device Entry Type Codes */
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#define IVHD_DEV_4_BYTE_ALL 0x01
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#define IVHD_DEV_4_BYTE_SELECT 0x02
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#define IVHD_DEV_4_BYTE_START_RANGE 0x03
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#define IVHD_DEV_4_BYTE_END_RANGE 0x04
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#define IVHD_DEV_8_BYTE_ALIAS_SELECT 0x42
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#define IVHD_DEV_8_BYTE_ALIAS_START_RANGE 0x43
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#define IVHD_DEV_8_BYTE_EXT_SELECT 0x70
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#define IVHD_DEV_8_BYTE_EXT_START_RANGE 0x71
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#define IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV 0x72
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#define IVHD_DEV_VARIABLE 0xF0
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/* IVHD Device Table Entry (DTE) Settings */
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#define IVHD_DTE_LINT_1_PASS (1 << 7)
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#define IVHD_DTE_LINT_0_PASS (1 << 6)
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#define IVHD_DTE_SYS_MGT_TGT_ABT (0 << 4)
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#define IVHD_DTE_SYS_MGT_NO_TRANS (1 << 4)
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#define IVHD_DTE_SYS_MGT_INTX_NO_TRANS (2 << 4)
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#define IVHD_DTE_SYS_MGT_TRANS (3 << 4)
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#define IVHD_DTE_NMI_PASS (1 << 2)
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#define IVHD_DTE_EXT_INT_PASS (1 << 1)
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#define IVHD_DTE_INIT_PASS (1 << 0)
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/* IVHD Device Entry Extended DTE Setting Field */
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#define IVHD_DEV_EXT_ATS_DISABLE (1 << 31)
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/* IVHD Special Device Entry Variety Field */
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#define IVHD_SPECIAL_DEV_IOAPIC 0x01
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#define IVHD_SPECIAL_DEV_HPET 0x02
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/* Device EntryType F0h UID Format */
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#define IVHD_UID_NOT_PRESENT 0x00
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#define IVHD_UID_INT 0x01
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#define IVHD_UID_STRING 0x02
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#endif
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