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soc/amd/picasso/acpi: remove AOAC device enables from global NVS 

These values in GNVS are written, but never read/used. aoac.asl contains
proper ACPI power management functions for the AOAC devices that
directly access the state from the device's registers instead of relying
on cached values in GNVS, so the corresponding GNVS entries can be
dropped.

BUG=b:161165393
TEST=Mandolin still boots and dmesg shows no new ACPI errors.

Change-Id: Iee78df215308bd9b656228be787fac121d10ca99
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2020-08-05 17:16:16 +02:00
parent 12bee2af23
commit b7594b09b5
3 changed files with 1 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/amd/picasso/acpi/globalnvs.asl
View File

@ -25,19 +25,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TMPS, 8, // 0x17 - Temperature Sensor ID TMPS, 8, // 0x17 - Temperature Sensor ID
TCRT, 8, // 0x18 - Critical Threshold TCRT, 8, // 0x18 - Critical Threshold
TPSV, 8, // 0x19 - Passive Threshold TPSV, 8, // 0x19 - Passive Threshold
Offset (0x20), // 0x20 - AOAC Device Enables
, 7,
IC2E, 1, // I2C2, 7
IC3E, 1, // I2C3, 8
IC4E, 1, // I2C4, 9
, 1,
UT0E, 1, // UART0, 11
UT1E, 1, // UART1, 12
, 3,
UT2E, 1, // UART2, 16
, 9,
UT23, 1, // UART3, 26
ESPI, 1, // ESPI, 27
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100), Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl> #include <vendorcode/google/chromeos/acpi/gnvs.asl>

4
src/soc/amd/picasso/include/soc/nvs.h
View File

@ -25,9 +25,7 @@ struct __packed global_nvs {
uint8_t tmps; /* 0x17 - Temperature Sensor ID */ uint8_t tmps; /* 0x17 - Temperature Sensor ID */
uint8_t tcrt; /* 0x18 - Critical Threshold */ uint8_t tcrt; /* 0x18 - Critical Threshold */
uint8_t tpsv; /* 0x19 - Passive Threshold */ uint8_t tpsv; /* 0x19 - Passive Threshold */
uint8_t pad1[6]; uint8_t unused[230];
aoac_devs_t aoac; /* 0x20 - AOAC device enables */
uint8_t unused[220];
/* ChromeOS specific (0x100 - 0xfff) */ /* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos; chromeos_acpi_t chromeos;

18
src/soc/amd/picasso/southbridge.c
View File

@ -347,22 +347,6 @@ void southbridge_init(void *chip_info)
al2ahb_clock_gate(); al2ahb_clock_gate();
} }
static void set_sb_final_nvs(void)
{
struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs == NULL)
return;
gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2);
gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3);
gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4);
gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0);
gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1);
gnvs->aoac.ut2e = is_aoac_device_enabled(FCH_AOAC_DEV_UART2);
gnvs->aoac.ut3e = is_aoac_device_enabled(FCH_AOAC_DEV_UART3);
gnvs->aoac.espi = 1;
}
void southbridge_final(void *chip_info) void southbridge_final(void *chip_info)
{ {
uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;
@ -370,8 +354,6 @@ void southbridge_final(void *chip_info)
if (CONFIG(MAINBOARD_POWER_RESTORE)) if (CONFIG(MAINBOARD_POWER_RESTORE))
restored_power = PM_RESTORE_S0_IF_PREV_S0; restored_power = PM_RESTORE_S0_IF_PREV_S0;
pm_write8(PM_RTC_SHADOW, restored_power); pm_write8(PM_RTC_SHADOW, restored_power);
set_sb_final_nvs();
} }
/* /*