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sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LP 

The Intel Basking Ridge CRB does not have a Lynxpoint LP PCH but was
using the lp gpio code instead of the southbridge/intel/common code in
verstage.

Change-Id: I775d3dc3540fbd8a939701d873183dd016e24ba4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2021-04-30 16:11:37 +02:00 committed by Patrick Georgi
parent c37d7b979f
commit b761903b8b
2 changed files with 2 additions and 1 deletions
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1
src/southbridge/intel/common/Makefile.inc
View File

@ -27,6 +27,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c
bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c

2
src/southbridge/intel/lynxpoint/Makefile.inc
View File

@ -41,10 +41,10 @@ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
ramstage-y += lp_gpio.c
smm-y += lp_gpio.c
verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c
endif
verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c
verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c
CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include