mb/google/kukui: Extend FMAP to 8MB layout
The SPI flash component requirement for Kukui family is 8M so we should update FMAP for that: - Add more comments for alignment and size recommendation. - Enlarge RO to 4M, and RW_SECTION_{A,B} both ~1.5M. - BOOTBLOCK: 32K->128K, aligned with other ARM boards. - Preserve RW_DDR_TRAINING for new calibration. - Reorder the sections for better alignment. - RW_MISC to contain RW sections that should be merged when creating AU image. BUG=b:134624821 TEST=Built Kukui image and boots. dump_fmap -h image-kukui.bin: # name start end size RW_LEGACY 00700000 00800000 00100000 RW_SHARED 006f7000 00700000 00009000 RW_UNUSED 006f8000 00700000 00008000 SHARED_DATA 006f7000 006f8000 00001000 RW_SECTION_B 00580000 006f7000 00177000 RW_FWID_B 006f6f00 006f7000 00000100 FW_MAIN_B 00582000 006f6f00 00174f00 VBLOCK_B 00580000 00582000 00002000 RW_MISC 00577000 00580000 00009000 RW_ELOG 0057f000 00580000 00001000 RW_DDR_TRAINING 0057d000 0057f000 00002000 RW_NVRAM 0057b000 0057d000 00002000 RW_VPD 00577000 0057b000 00004000 RW_SECTION_A 00400000 00577000 00177000 RW_FWID_A 00576f00 00577000 00000100 FW_MAIN_A 00402000 00576f00 00174f00 VBLOCK_A 00400000 00402000 00002000 WP_RO 00000000 00400000 00400000 RO_VPD 003f8000 00400000 00008000 RO_SECTION 00000000 003f8000 003f8000 RO_FRID 003f7f00 003f8000 00000100 GBB 003f5000 003f7f00 00002f00 COREBOOT 00021000 003f5000 003d4000 FMAP 00020000 00021000 00001000 BOOTBLOCK 00000000 00020000 00020000 Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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FLASH@0x0 0x800000 {
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# Firmware Layout Description for Chrome OS.
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WP_RO@0x0 0x200000 {
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#
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RO_SECTION@0x0 0x1f8000 {
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# The size and address of every section must be aligned to at least 4K, except:
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BOOTBLOCK@0 32K
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# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
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FMAP@0x8000 0x1000
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#
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COREBOOT(CBFS)@0x9000 0x1ec000
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# 'FMAP' may be found by binary search so its starting address should be better
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# aligned to larger values.
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#
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# For sections to be preserved on update, add (PRESERVE) to individual sections
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# instead of a group section; otherwise the preserved data may be wrong if you
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# resize or reorder sections inside a group.
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FLASH@0x0 8M {
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WP_RO@0x0 4M {
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RO_SECTION {
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BOOTBLOCK 128K
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FMAP 4K
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COREBOOT(CBFS)
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GBB 0x2f00
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GBB 0x2f00
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RO_FRID 0x100
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RO_FRID 0x100
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}
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}
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RO_VPD(PRESERVE)@0x1f8000 0x8000
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RO_VPD(PRESERVE) 32K # At least 16K.
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}
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}
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RW_SECTION_A@0x200000 0x7c000 {
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RW_SECTION_A 1500K {
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VBLOCK_A@0x0 0x2000
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VBLOCK_A 8K
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FW_MAIN_A(CBFS) 0x79f00
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FW_MAIN_A(CBFS)
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RW_FWID_A 0x100
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RW_FWID_A 0x100
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}
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}
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RW_SHARED@0x27c000 0x1000 {
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RW_MISC 36K {
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SHARED_DATA@0x0 0x1000
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RW_VPD(PRESERVE) 16K # At least 8K.
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RW_NVRAM(PRESERVE) 8K
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RW_DDR_TRAINING(PRESERVE) 8K
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RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K.
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}
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}
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RW_NVRAM(PRESERVE)@0x27d000 0x2000
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RW_SECTION_B 1500K {
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# ELOG driver has hard-coded the size to 4k.
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VBLOCK_B 8K
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RW_ELOG(PRESERVE)@0x27f000 0x1000
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FW_MAIN_B(CBFS)
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RW_SECTION_B@0x280000 0x7c000 {
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VBLOCK_B@0x0 0x2000
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FW_MAIN_B(CBFS) 0x79f00
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RW_FWID_B 0x100
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RW_FWID_B 0x100
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}
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}
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RW_VPD(PRESERVE)@0x2fc000 0x4000
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RW_SHARED 36K { # Will be force updated on recovery.
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RW_LEGACY(CBFS)@0x300000 0x100000
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SHARED_DATA 4K # 4K or less for netboot params.
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RW_UNUSED
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}
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RW_LEGACY(CBFS) 1M # Minimal 1M.
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}
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}
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