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soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabled 

FSP has recently added support for a UPD switch to power gate SATA. This
change adds the coreboot side of the feature. To avoid having two SATA
enable options, the value of the sata_enable UPD is determined by the
enable state of the AHCI controller in the platform devicetree.

BUG=b:162302027
BRANCH=zork
TEST=Verify AHCI controller can be hidden/disabled.

Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt Papageorge 2020-07-30 15:22:46 -05:00 committed by Furquan Shaikh
parent b1c7ed326a
commit b87effe1dd
1 changed files with 24 additions and 0 deletions
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24
src/soc/amd/picasso/romstage.c
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@ -64,6 +64,29 @@ static bool devtree_hda_dev_enabled(void)
}
static const struct device_path sata_path[] = {
{
.type = DEVICE_PATH_PCI,
.pci.devfn = PCIE_GPP_B_DEVFN
},
{
.type = DEVICE_PATH_PCI,
.pci.devfn = SATA_DEVFN
},
};
static bool devtree_sata_dev_enabled(void)
{
const struct device *ahci_dev;
ahci_dev = find_dev_nested_path(pci_root_bus(), sata_path, ARRAY_SIZE(sata_path));
if (!ahci_dev)
return false;
return ahci_dev->enabled;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
@ -115,6 +138,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope;
mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset;
mcfg->hd_audio_enable = devtree_hda_dev_enabled();
mcfg->sata_enable = devtree_sata_dev_enabled();
}
asmlinkage void car_stage_entry(void)