drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driver

The common cbmem_top_chipset implementation uses the FSP bootloader HOB,
thus move it to the fsp driver which is a more appropriate place.

Change-Id: I914df51a7414eb72416f816ff8375a13d5716925
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36620
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2019-11-04 22:13:44 +01:00 committed by Nico Huber
parent 46e68ac99a
commit b8cd4b0049
10 changed files with 1 additions and 14 deletions

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@ -22,6 +22,7 @@ romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
romstage-y += util.c
romstage-y += memory_init.c
romstage-$(CONFIG_MMA) += mma_core.c
romstage-y += cbmem.c
ramstage-y += debug.c
ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c

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@ -84,7 +84,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SRAM
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_INTEL_COMMON_BLOCK_SCS
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_TCO

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@ -88,7 +88,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA

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@ -3,12 +3,6 @@ config SOC_INTEL_COMMON_BLOCK_SA
help
Intel Processor common System Agent support
config SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
bool
help
Select this if you want cbmem_top_chipset use the TOLUM returned
by the FSP HOB.
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000

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@ -6,4 +6,3 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c
postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM) += cbmem.c

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@ -47,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_PMC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
# select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_PCR

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@ -43,7 +43,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_SA

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@ -32,8 +32,6 @@ config CPU_SPECIFIC_OPTIONS
select PLATFORM_USES_FSP2_0
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_SETS_MSRS
select SPI_FLASH
select UART_OVERRIDE_REFCLK

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@ -58,7 +58,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL