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mb/google/zork: update GPIO config for dirinboz 

dirinboz does not support stylus, config AGPIO4/5 to NC
to prevent unexpected wake event for s3.

BUG=none
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44894
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kevin Chiu 2020-08-28 11:56:31 +08:00 committed by Patrick Georgi
parent cf081ab58c
commit b91e518062
1 changed files with 13 additions and 2 deletions
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15
src/mainboard/google/zork/variants/dirinboz/gpio.c
View File

@ -8,6 +8,10 @@
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
/* PEN_DETECT_ODL - no used */
PAD_NC(GPIO_4),
/* PEN_POWER_EN - no used */
PAD_NC(GPIO_5),
/* TP */ /* TP */
PAD_NC(GPIO_32), PAD_NC(GPIO_32),
/* EN_DEV_BEEP_L */ /* EN_DEV_BEEP_L */
@ -16,6 +20,13 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
PAD_GPO(GPIO_140, HIGH), PAD_GPO(GPIO_140, HIGH),
}; };
static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = {
/* PEN_DETECT_ODL - no used */
PAD_NC(GPIO_4),
/* PEN_POWER_EN - no used */
PAD_NC(GPIO_5),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{ {
uint32_t board_version; uint32_t board_version;
@ -33,6 +44,6 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
return bid_1_gpio_set_stage_ram; return bid_1_gpio_set_stage_ram;
} }
*size = 0; *size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram);
return NULL; return dirinboz_gpio_set_stage_ram;
} }