mb/google/zork: update GPIO config for dirinboz
dirinboz does not support stylus, config AGPIO4/5 to NC to prevent unexpected wake event for s3. BUG=none BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44894 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -8,6 +8,10 @@
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#include <ec/google/chromeec/ec.h>
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static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
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/* PEN_DETECT_ODL - no used */
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PAD_NC(GPIO_4),
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/* PEN_POWER_EN - no used */
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PAD_NC(GPIO_5),
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/* TP */
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PAD_NC(GPIO_32),
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/* EN_DEV_BEEP_L */
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@ -16,6 +20,13 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
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PAD_GPO(GPIO_140, HIGH),
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};
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static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = {
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/* PEN_DETECT_ODL - no used */
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PAD_NC(GPIO_4),
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/* PEN_POWER_EN - no used */
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PAD_NC(GPIO_5),
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};
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const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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{
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uint32_t board_version;
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@ -33,6 +44,6 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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return bid_1_gpio_set_stage_ram;
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}
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*size = 0;
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return NULL;
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*size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram);
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return dirinboz_gpio_set_stage_ram;
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}
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