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soc/amd/sabrina: enable warm reset functionality 

Commit 3e1943ec46 (soc/amd/cezanne: Force
resets to be cold) forced all resets on Cezanne to be cold resets to
work around a bug. Since the bug is fixed on Sabrina, this workaround
copied over from the Cezanne code isn't needed here, so sort-of revert
what the patch referenced above changed for Cezanne in the Sabrina code.

BUG=b:229105416

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I785e43124a9a969eeb129454e6e15dc245625250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Felix Held 2022-04-20 14:08:09 +02:00
parent 9077d65b5b
commit b94d3681e1
2 changed files with 1 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/amd/sabrina/fch.c
View File

@ -127,11 +127,6 @@ static void fch_init_acpi_ports(void)
PM_ACPI_TIMER_EN_EN); PM_ACPI_TIMER_EN_EN);
} }
static void fch_init_resets(void)
{
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
}
/* configure the general purpose PCIe clock outputs according to the devicetree settings */ /* configure the general purpose PCIe clock outputs according to the devicetree settings */
static void gpp_clk_setup(void) static void gpp_clk_setup(void)
{ {
@ -198,7 +193,6 @@ static void cgpll_clock_gate_init(void)
void fch_init(void *chip_info) void fch_init(void *chip_info)
{ {
fch_init_resets();
i2c_soc_init(); i2c_soc_init();
fch_init_acpi_ports(); fch_init_acpi_ports();

4
src/soc/amd/sabrina/reset.c
View File

@ -19,9 +19,7 @@ void do_cold_reset(void)
void do_warm_reset(void) void do_warm_reset(void)
{ {
/* Warm resets are not supported and must be executed as cold */ /* Assert reset signals only. */
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
TOGGLE_ALL_PWR_GOOD);
outb(RST_CPU | SYS_RST, RST_CNT); outb(RST_CPU | SYS_RST, RST_CNT);
} }