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nb/intel/gm45/northbridge.c: Use `MiB` definition 

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Ibfa9a6fa7818d0bd79d2c0d9331c0ca38a2b7fe3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Angel Pons 2020-08-03 15:11:55 +02:00
parent b053583a1c
commit b9bbed2c41
1 changed files with 4 additions and 3 deletions
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7
src/northbridge/intel/gm45/northbridge.c
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@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> #include <cbmem.h>
#include <commonlib/helpers.h>
#include <console/console.h> #include <console/console.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
@ -37,15 +38,15 @@ static int decode_pcie_bar(u32 *const base, u32 *const len)
switch ((pciexbar_reg >> 1) & 3) { switch ((pciexbar_reg >> 1) & 3) {
case 0: /* 256MB */ case 0: /* 256MB */
*base = pciexbar_reg & (0x0f << 28); *base = pciexbar_reg & (0x0f << 28);
*len = 256 * 1024 * 1024; *len = 256 * MiB;
return 1; return 1;
case 1: /* 128M */ case 1: /* 128M */
*base = pciexbar_reg & (0x1f << 27); *base = pciexbar_reg & (0x1f << 27);
*len = 128 * 1024 * 1024; *len = 128 * MiB;
return 1; return 1;
case 2: /* 64M */ case 2: /* 64M */
*base = pciexbar_reg & (0x3f << 26); *base = pciexbar_reg & (0x3f << 26);
*len = 64 * 1024 * 1024; *len = 64 * MiB;
return 1; return 1;
} }