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asrock/imb-a180: Switch away from ROMCC_BOOTBLOCK

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Change-Id: I603e6c83d72cf6c1d8f8c6eef652fdf954a3a284
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37453
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-12-03 13:32:11 +02:00
parent a73317e5cf
commit b9edd8be67
3 changed files with 7 additions and 22 deletions
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1
src/mainboard/asrock/imb-a180/Kconfig
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@ -17,7 +17,6 @@ if BOARD_ASROCK_IMB_A180
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select ROMCC_BOOTBLOCK
select CPU_AMD_AGESA_FAMILY16_KB select CPU_AMD_AGESA_FAMILY16_KB
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE select SOUTHBRIDGE_AMD_AGESA_YANGTZE

2
src/mainboard/asrock/imb-a180/Makefile.inc
View file

@ -13,6 +13,8 @@
# GNU General Public License for more details. # GNU General Public License for more details.
# #
bootblock-y += bootblock.c
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c romstage-y += OemCustomize.c

26
src/mainboard/asrock/imb-a180/romstage.c → src/mainboard/asrock/imb-a180/bootblock.c
View file

@ -1,8 +1,6 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License. * the Free Software Foundation; version 2 of the License.
@ -13,35 +11,21 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <stdint.h> #include <amdblocks/acpimmio.h>
#include <device/pci_def.h> #include <bootblock_common.h>
#include <arch/io.h> #include <device/pnp_type.h>
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627uhg/w83627uhg.h> #include <superio/winbond/w83627uhg/w83627uhg.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
void board_BeforeAgesa(struct sysinfo *cb) void bootblock_mainboard_early_init(void)
{ {
volatile u32 *addr32; volatile u32 *addr32;
u32 t32; u32 t32;
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
/* Enable the AcpiMmio space */
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
outb(0xea, 0xcd6); pm_write8(0xea, 0x1);
outb(0x1, 0xcd7);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
addr32 = (u32 *)0xfed80e28; addr32 = (u32 *)0xfed80e28;