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mb/google/sarien/variants/sarien: Adjust TP/TS I2C CLK to meet spec 

After adjustment on Sarien EVT
Touch Screen CLK (Elan):  389.7 KHz
Touch Screen CLK (Melfas): 377.7 KHz
Touch Pad CLK: 385 KHz

BUG=b:122657195
BRANCH=master
TEST=emerge-sarien coreboot chromeos-bootimage
     measure by scope with sarien.

Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: I53b60354e5a7a0ace8efb677775c0a9f8779061d
Reviewed-on: https://review.coreboot.org/c/31476
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris Zhou 2019-02-19 15:56:15 +08:00 committed by Duncan Laurie
parent 34745f613f
commit ba269fd77e
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/sarien/variants/sarien/devicetree.cb
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@ -157,12 +157,12 @@ chip soc/intel/cannonlake
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 190,
.fall_time_ns = 120,
.rise_time_ns = 100,
.fall_time_ns = 80,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 52,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
.i2c[4] = {