mb/google/hatch/var/scout: set correct i2c configuration
Scout only uses I2C 1, 2, and 3 in DVT units. This removes extraneous I2C configuration copied from Puff. BUG=b:202195805 TEST=Boot scout, verify no more errors due to missing I2C devices Change-Id: Ide70a53e83b3e14540873062e3bef24d1134d2e1 Signed-off-by: Matt Ziegelbaum <ziegs@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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@ -51,16 +51,14 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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/* C15 : WLAN_OFF_L */
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PAD_CFG_GPO(GPP_C15, 1, DEEP),
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/*
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* TODO(b/187094460): Re-enable touch screen I2C after resolving USB
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* conflict
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*/
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/* C16 : PCH_I2C_RFU_SDA (NC) */
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PAD_NC(GPP_C16, NONE),
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/* C17 : PCH_I2C_RFU_SCL (NC) */
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PAD_NC(GPP_C17, NONE),
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/* C18 : PCH_I2C_USI_SDA */
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PAD_NC(GPP_C18, NONE),
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* C19 : PCH_I2C_USI_SDL */
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PAD_NC(GPP_C19, NONE),
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* D13 : SMBUS_ISP_SCALAR */
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PAD_CFG_GPO(GPP_D13, 0, DEEP),
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@ -112,14 +110,22 @@ static const struct pad_config gpio_table[] = {
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/* F22 : EMMC_RST_L */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* H4: PCH_I2C_PCON_SDA */
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/* H4: PCH_I2C_SCALER_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5: PCH_I2C_PCON_SCL */
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/* H5: PCH_I2C_SCALER_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H6 : PCH_I2C_TPU_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : PCH_I2C_TPU_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H8 : NC */
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PAD_NC(GPP_H8, NONE),
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/* H9 : NC */
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PAD_NC(GPP_H9, NONE),
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/* H10 : NC */
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PAD_NC(GPP_H10, NONE),
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/* H11 : NC */
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PAD_NC(GPP_H11, NONE),
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/* H22 : PWM_PP3300_BIOZZER */
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PAD_CFG_GPO(GPP_H22, 0, DEEP),
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};
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@ -4,11 +4,11 @@ chip soc/intel/cannonlake
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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[PchSerialIoIndexSPI0] = PchSerialIoPci,
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[PchSerialIoIndexSPI1] = PchSerialIoPci,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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@ -150,20 +150,19 @@ chip soc/intel/cannonlake
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| I2C0 | RFU |
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#| I2C2 | PS175 |
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#| I2C3 | MST |
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#| I2C4 | Audio |
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#| I2C1 | USI (Touch screen) |
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#| I2C2 | SCALER |
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#| I2C3 | TPU |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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@ -175,11 +174,6 @@ chip soc/intel/cannonlake
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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}"
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# PCIe root port 7 for LAN
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@ -380,24 +374,11 @@ chip soc/intel/cannonlake
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device pci 15.0 off
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# RFU - Reserved for Future Use.
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end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2, PCON PS175.
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device pci 15.3 off end # I2C #3, Realtek RTD2142.
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device pci 15.1 on end # I2C #1, USI (Touch screen)
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device pci 15.2 on end # I2C #2, SCALER
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device pci 15.3 on end # I2C #3, TPU
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device pci 16.0 on end # Management Engine Interface 1
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device pci 19.0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5682""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
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register "property_count" = "1"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end #I2C #4
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device pci 19.0 off end # I2C #4
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device pci 1a.0 on end # eMMC
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device pci 1c.6 on # PCI Root Port 7 (LAN)
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chip drivers/net # RTL8111H Ethernet NIC
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